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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

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    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
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    • Coding Guidelines & Deployment

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    • Coverage Cookbook

      • Introduction
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      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
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      • Low Power Verification - 4/29
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • Mentor Graphics Announces EZ-VIP Package for Enhanced Testbench Productivity

Mentor Graphics Announces EZ-VIP Package for Enhanced Testbench Productivity

WILSONVILLE, Ore., June 2, 2015 - Mentor Graphics Corporation (NASDAQ: MENT) today announced the immediate availability of the EZ-VIP productivity package for ASIC and FPGA verification teams using Questa® Verification IP (QVIP). This package increases productivity by reducing the time spent creating, instantiating, configuring and connecting up a QVIP testbench by 5X or more. This means verification teams have more time available to use QVIP to verify that their design is functionally correct.

The EZ-VIP package consists of QVIP Configurator software, a VIP bring up service package and a new EZ-VIP API. The QVIP Configurator software creates, instantiates and configures UVM testbenches for all protocols in the QVIP library, including PCIe, AMBA, USB, Ethernet, MIPI and Memory protocols, avoiding the time-consuming and error-prone process of writing these testbenches by hand. In many verification projects, a complicated end-to-end UVM verification infrastructure has to be created before a single test can be written. The bring up service package leverages the Mentor® protocol expertise and experience to allow project teams to start from a working, connected end to end testbench. This means verification teams can be productive writing tests immediately. The new EZ-VIP API provides easy-to-use stimulus, transaction logging, and delay control, so that test writers can focus on the behavior of their tests without being delayed by the complexity of UVM.

 “We have been highly productive using Mentor’s QVIP library,” said Sundararajan Haran, engineering manager of logic verification and ASIC for Microsemi Corporation. “With other tools in Mentor’s Enterprise Verification Platform such as Questa Portable Stimulus Solutions combined with VIP, Verification Management and Formal Solutions, we have been able to rapidly verify different configurations for our SoC FPGA product families.”

The Questa VIP library provides engineers with standard UVM SystemVerilog (SV) components using a common architecture across all supported protocols. This allows rapid deployment of multiple protocols within a verification team. Test plans, compliance tests, test sequences and protocol coverage are all included as SV and XML source code, allowing simple re-use, extension and debug. The Mentor VIP components also include a comprehensive set of protocol checks, error injection and debug capabilities.

“Verification IP is key component of our Enterprise Verification Platform, which provides a complete verification solution from virtual prototyping to simulation, emulation, FPGA prototyping and post-silicon debug,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “The EZ-VIP productivity package means that our customers can achieve their verification goals quickly and reliably.”

About the Questa Functional Verification platform

The Questa Functional Verification platform is a core technology in the Mentor Enterprise Verification Platform (EVP) – a platform that boosts productivity in ASIC, FGPA and SoC functional verification by combining advanced verification technologies in a comprehensive platform.

(Mentor Graphics, Mentor and Questa are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

For more information

Carole Dunn
carole_dunn@mentor.com
Mentor Graphics
503-685-4716

Related Products

Mentor Verification IP

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About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.24 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

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