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Verification Horizons Blog

Verification Knowledge Exchange.
In this BLOG you will find posts from the Verification Academy's Harry Foster, Verification Horizon's Tom Fitzpatrick and Standard's Advocate Dennis Brophy and a host of other Verification Horizon Contributors.

The Verification Horizons Blog will provide an online forum for updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Latest blog post: UVM Debug. A contest using class based testbench debug… - Rich Edelman

Additional blog posts include:

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Upcoming Verification Events

May:

  • New School Coverage Closure - Online | May 28th

    Management of complex SoC development projects to the point of successful coverage closure has become a very challenging job. Design and verification engineers spend enormous amounts of time reviewing coverage holes. This presentation discusses a new school formal verification method which automates the job of focusing coverage closure efforts on the items which actually need to be hit and the results achieved on a large SoC design in the entertainment and signal processing domain.

June:

  • Verification Academy at DAC - San Francisco | June 8th - 11th

    Visit the Verification Academy booth #2408 on the DAC exhibit floor where Mentor will be digging deeper into the challenges of IC Design and Verification with presentations and lively conversation.

  • Trends in FPGA and ASIC/IC Functional Verification - Online | June 16th

    This web seminar presents the most recent ASIC/IC Verification Trends findings from the 2014 Wilson Research Group and Mentor Graphics industry study on functional verification.

  • Mentor Functional Verification Forum - Hsinchu, Taiwan | June 18th

    Sessions include: Faster, Stronger, and Smarter - Mentor Enterprise Verification Platform, Visualizer Debug Environment for RTL and UVM, New Hierarchical Clock-Domain Crossing (CDC) Flow and more!

  • New School Connectivity Checking - Online | June 30th

    One of the primary goals of SoC-level verification is to ensure that all top-level connections have been made correctly. However, this is no easy task. Today's SoC designs contain large numbers of design IP blocks, interconnected through multiple on-chip bus fabrics and point-to-point connections, which can result in interconnect signals that number in the thousands. This session discusses the use of a new school formal verification method which can be easily applied to solve the problem of connectivity checking with detailed case studies of how this formal app was used to automatically verify connectivity and accelerate the debug process.

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Verification Academy Technology Web Seminar Series

Join the Verification Academy technology experts each month for this online series. This series will feature sessions discussing the very latest on coverage closure, stimulus generation, fast and efficient VIP, debug techniques that will help you answer the age old question "am I done yet", details for designing an efficient UVM Testbench, new approaches for Software Driven Verification and more!

Web seminar topics include:

  • New School Thinking for Fast and Efficient Verification Using EZ-VIP

    With the complexity and interoperability needs of today's systems the use of standard interfaces such as PCIe and MIPI is a must. Verification of IP to implement these interfaces for re-use within a wide variety of systems can be time consuming and hard to get right. Users of IP are often faced with issues of integration and getting caught in the complex details of the IP implementation when their real goal is to verify design specific and system functionality. Verification IP is available to solve these issues, but too often comes with a high integration effort and a steep learning curve of its own that users must overcome before they can become truly productive.

    This webinar will cover the use of UVM based verification IP for protocols such as PCI Express and MIPI CSI and DSI

  • New School Coverage Closure - Register | May 28th | 8:00 AM US/Pacific

    Management of complex SoC development projects to the point of successful coverage closure has become a very challenging job. Design and verification engineers spend enormous amounts of time reviewing coverage holes. This presentation discusses a new school formal verification method which automates the job of focusing coverage closure efforts on the items which actually need to be hit and the results achieved on a large SoC design in the entertainment and signal processing domain.

  • New School Connectivity Checking - Register | June 30th | 8:00 AM US/Pacific

    One of the primary goals of SoC-level verification is to ensure that all top-level connections have been made correctly. However, this is no easy task. Today's SoC designs contain large numbers of design IP blocks, interconnected through multiple on-chip bus fabrics and point-to-point connections, which can result in interconnect signals that number in the thousands. This session discusses the use of a new school formal verification method which can be easily applied to solve the problem of connectivity checking with detailed case studies of how this formal app was used to automatically verify connectivity and accelerate the debug process.

  • New School Stimulus Generation Techniques - Register | July 9th | 8:00 AM US/Pacific

    Techniques for generating verification stimulus have been around as long there have been designs to verify. As the designs being verified have become more complex, stimulus generation techniques have evolved to address the emerging requirements. From directed tests to random test generation to graph-based intelligent testbench automation, development of these stimulus generation techniques has evolved from specific verification challenges. The development of a new stimulus generation technique rarely results in the obsolescence of previously-created stimulus generation techniques. Picking the right stimulus generation techniques to use is crucial to efficiently achieving quality functional verification results. This session will explore the three dominant stimulus generation techniques used today for functional verification to identify; the characteristics of stimulus generated by each technique, where each technique best applies on its own and how these new school techniques can be combined to achieve even greater verification value.

  • Evolution of Debug - Register | July 28th | 8:00 AM US/Pacific

  • The debug activity takes a significant proportion of any design or verification engineer's time and there is much we in the Design Automation industry can do to improve individual and team productivity in this area. It starts with putting ourselves in the users' shoes and designing a complete solution, not just 80% of a solution. Gordon Allan takes a critical look at the past, present and future challenges for debug, exploring real world situations drawn from years of experience in SoC design and verification, and describing leading-edge techniques and compelling solutions.

    New School Regression Control - Register | August 27th | 8:00 AM US/Pacific

    Getting the very best from your verification resources requires a regression system that understands the verification process and is tightly integrated with Workload Management and Distributed Resource Management software. Both requirements depend on visibility into available software and hardware resources, and by combining their strengths, users can massively improve productivity by reducing unnecessary verification cycles.

    This session will show how adding control and visibility to these systems, and then better integrating them, will help your organization get the very best from every verification dollar. It will also highlight how separating control from the configuration data in a regression system improves maintenance and user productivity. Major features can be coded into the system itself instead of added as a series of scripts with multiple calling levels, which often lead to a debug nightmare.

  • New Low Power Verification Techniques - Register | September 10th | 8:00 AM US/Pacific

  • IEEE 1801 UPF enables specification of power intent early in the design flow, to drive both verification and implementation processes. But power management decisions must be made incrementally throughout the flow, often by different people at each stage. Power intent specifications need to be structured in a manner that reflects these stages, to organize the information effectively, to ensure clear communication among IP providers, designers, and implementers, and to maximize reuse of power intent. This session highlights a "new school" low power methodology termed "successive refinement" that uses the strength of UPF in just such a structured approach. It will explain what kinds of power intent information should be captured at each stage, which features of UPF are involved in doing so, and how this structured approach benefits both IP providers and IP users.

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Featured Papers & Posters from DVCon 2015

The following papers were presented at DVCon 2015.

Goldilocks and System Performance Modeling - A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology

  • Presenter: Rich Edelman - Mentor Graphics

Jump-Start Software-Driven Hardware Verification with a Verification Framework

  • Presenter: Matthew Ballance - Mentor Graphics

Want a Boost in Your Regression Throughput? Simulate Common Setup Phase Only Once

  • Presenter: Rohit K. Jain - Mentor Graphics

Are You Smarter Than Your Testbench? With a Little Work You Can Be

  • Presenter: Rich Edelman – Mentor Graphics

Coverage Data Exchange Is No Robbery, Or Is It?

  • Presenters: Thom Ellis, Darron May - Mentor Graphics

The Big Brain Theory - Visualizing SoC Design & Verification Data

  • Presenter: Gordon Allan - Mentor Graphics

Successive Refinement: A Methodology for Incremental Specification of Power Intent

  • Presenter: Erich Marschner - Mentor Graphics

Portable Stimulus Models for C/SystemC, UVM and Emulation

  • Authors: Mike Andrews - Mentor Graphics, Boris Hristov - Ciena

Unleashing the Full Power of UPF Power States

  • Authors: Erich Marschner - Mentor Graphics, John Biggs - ARM® Ltd.

UVM Sans UVM - An Approach to Automating UVM Testbench Writing

  • Authors: Rich Edelman, Shashi Bhutada - Mentor Graphics

Addressing the Challenges of Reset Verification in SoC Designs

  • Authors: Chris Kwok, Priya Viswanathan, Ping Yeung - Mentor Graphics

Multi-Domain Verification: When Clock, Power and Reset Domains Collide

  • Authors: Ping Yeung, Erich Marschner - Mentor Graphics

Not Just for Hardware Debug: Prototype Debuggers for System Validation and Optimization

  • Presenter: Michael Sachtjen - Mentor Graphics

A Simplified and Reusable UVM Config DB Methodology for Environment Developers and Test Writers Alike

  • Presenter: Robert D. Oden - Mentor Graphics

Debug Challenges in Low-Power Design and Verification

  • Presenter: Jitesh Bansal - Mentor Graphics

The UPF 2.1 Library Commands: Truly Unifying the Power Specification Formats

  • Presenter: Amit Srivastava - Mentor Graphics

Next-Generation Power Aware CDC Verification – What Have We Learned?

  • Presenter: Kurt Takara - Mentor Graphics

PA-APIs: Looking Beyond Power Intent Specification Formats

  • Presenter: Amit Srivastava - Mentor Graphics

Let's DisCOVER Power States

  • Presenter: Pankaj K. Dwivedi - Mentor Graphics

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Mentor Graphics Acquires Flexras Technologies

WILSONVILLE, Ore., January 13, 2015 — Mentor Graphics Corp. (NASDAQ: MENT) today announced that it has acquired Flexras Technologies, a leading developer of proprietary technologies that reduce time required for prototyping, validation, and debug of integrated circuits (ICs) and systems on chip (SoCs).  Flexras timing-driven partitioning technology will expand and strengthen the portfolio of tools available from Mentor to help engineers overcome the challenges of increasingly complex design prototyping.

“We’re extremely pleased to have the Flexras team join Mentor Graphics,” said John Lenyo, vice president and general manager of the Mentor Design Verification Technology Division. “We’re committed to helping our customers reduce the risks and costs associated with design prototyping and Flexras has proven to be a visionary in this area.”

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Mentor Graphics Announces New Verification IP for PCIe 4.0

WILSONVILLE, Ore., December 8, 2014 – Mentor Graphics Corp. (Nasdaq: MENT) today announced the immediate availability of its new Mentor® EZ-VIP PCI Express Verification IP. The new Verification IP (VIP) reduces testbench assembly time for ASIC (application-specific integrated circuit) and FPGA (field-programmable gate array) design verification by a factor of up to 10X.

Verification IP is intended to help engineers reduce the time spent building testbenches by providing re-usable building blocks for common protocols and architectures.  However, even standard protocols and common architectures can be configured and implemented differently from design to design.  As a result, traditional VIP components can take days, or even weeks, to prepare for a simulation or emulation testbench.

 “When designing with the ARMv8-A architecture and ARM® CoreLink™ cache coherent interconnects in mobile, networking and server SoCs, our partners have a choice of PCIe root complex solutions,” said Jim Wallace, director, systems and software group, ARM®. “ARM® has used Mentor’s PCIe VIP library running on Questa® and Veloce® to help verify critical interactions between PCIe and ARM® AMBA® interface domains to enable rapid deployment and accurate protocol checking.”

Unlike traditional verification IP, Mentor’s new PCIe EZ-VIP is “design-aware,” eliminating several time-consuming steps in the testbench assembly process.  This fast-forwards verification engineers past tedious configuration and implementation set-up tasks, directly to high-value scenario generation, reducing a process that used to take days or weeks to just hours.

“We have been pleased to collaborate with Mentor to support the validation of PCIe EZ-VIP,” said Stephane Hauradou, CTO of PLDA.  “After being one of the first PCIe providers to very quickly develop and introduce PCIe 3.0 and PCIe 4.0 controllers to ASIC and verification engineers, PLDA is pleased to combine silicon proven XpressRICH3 and XpressRICH4 IPs with PCIe EZ-VIP as a reliable, highly configurable and easy-to-use complete solution for ASIC project teams.”

“Having easy-to-use, pre-qualified PCIe Verification IP is very important for our customers. We have worked with Mentor to help them validate their PCIe EZ-VIP with our Expresso 3.0 core,” said Brian Daellenbach, president of Northwest Logic. “Consequently, customers can use the Mentor PCIe VIP with our silicon-proven PCI Express cores to create and verify their designs with high confidence.”

Mentor’s PCIe EZ-VIP includes pre-packaged, easy-to-use verification environments for the serial and parallel interfaces of PCIe 1.0, 2.0, 3.0, 4.0 and mPCIe, which can be used to verify PHY, Root Complex and Endpoint designs.  Test plans, compliance tests, test sequences, and protocol coverage are all included as SV and XML source code, allowing simple re-use, extension and debug. The Mentor VIP components also include a comprehensive set of protocol checks, error injection and debug capabilities.

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Verification Cookbook Seminars

Web Seminar Series featuring the Verification Methodology Cookbook.

The Verification Methodology Cookbook is an encyclopedia of Verification Methodology and is utilized by Verification Engineers across the globe to stay current with UVM, OVM and Coverage.

This series of online seminars, will focus on a featured "recipe" guiding users into a deeper understanding of the material.

Web seminar recipes include:

  • UVM Sequences in Depth

    The benefits that UVM provides in specifying modular reusable testbenches have been well documented. Regardless of these benefits, however, the need to adequately model functional coverage, and efficiently create stimuli to reach your coverage goals, remains. The use of UVM sequences allows encapsulation of constrained-random stimulus that can be reused, and virtual sequences allow composition to orchestrate stimuli on multiple interfaces to your DUT.

    This web seminar will introduce you to abstract stimulus specification to provide more effective UVM tests that can be reused throughout your SoC flow and show you how Questa employs intelligent automation to achieve coverage closure faster.

  • UVM 1.2 is Coming, So Be Prepared

    You may have heard there's a new version of UVM that's about to be released. This Verification Cookbook seminar will teach you everything you need to know about the future of UVM. We'll briefly cover the new features included in UVM1.2 and assess their impact on a typical verification environment, including performance and backward-compatibility concerns. We'll then review some UVM Coding Guidelines from the UVM Cookbook that will minimize the impact of these changes and close with a discussion of the UVM standardization process moving forward, including the future of UVM as an IEEE standards.

  • Mentor VIP, More than just a BFM

    Today's advanced UVM environments require more than a standard BFM to support environment reuse, randomized stimulus, generation of traffic scenarios, coverage collection, etc. For UVM environment infrastructure Questa VIP supports the operating modes required for block to top environment reuse as well as transaction monitoring and capturing from interfaces at any level of hierarchy within your design. For stimulus generation Questa VIP provides sequences and scenarios for constrained random generation as well as integration with the inFact algorithmic stimulus generation. For coverage closure Questa VIP also provides coverage models and test plans to help ensure adequate testing. These features allow verification teams to reuse design checking provided by environments and reuse coverage models from block level to top level simulation to accelerate coverage closure.

  • Raising Productivity Using Abstract UVM Stimulus and Intelligent Automation

    The benefits that UVM provides in specifying modular reusable testbenches have been well documented. Regardless of these benefits, however, the need to adequately model functional coverage, and efficiently create stimuli to reach your coverage goals, remains. The use of UVM sequences allows encapsulation of constrained-random stimulus that can be reused, and virtual sequences allow composition to orchestrate stimuli on multiple interfaces to your DUT.

    This web seminar will introduce you to abstract stimulus specification to provide more effective UVM tests that can be reused throughout your SoC flow and show you how Questa employs intelligent automation to achieve coverage closure faster.

  • Automating the Creation of Your UVM Register Model

    The UVM Register Layer is a great way to abstract the interaction between your testbench and your DUT from the pin-level, or even protocol-specific transactions to a generic register-based view of communication. This abstraction provides many benefits, not the least of which is isolating your stimulus generation and coverage modeling from low-level changes in your design (i.e. separating the what from the how). Unfortunately, the benefits of using the register layer come at the cost of having to specify the register models in your testbench to reflect the registers in your hardware. With thousands or even tens of thousands of registers in a typical design, this can be a laborious and error-prone process when done from scratch. This UVM Recipe of the Month will introduce the Register Assistant feature of the Questa Verification Platform and show how it can be used to quickly generate correct-by-construction register models and tests from a register specification.

  • Advanced UVM Debug

    The use of UVM and SystemVerilog to create object-oriented testbenches has magnified the need for a good debugging solution to allow engineers to focus on verifying the design, not fixing problems in the testbench. This web seminar will highlight some new strategies for debugging UVM-based testbenches.

  • Beyond UVM: Effectively Modeling and Analyzing Coverage

    This archived web seminar will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage, and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret. From there, we will review several examples that illustrate effective functional coverage for various applications, including bus protocol coverage, register-based block-level coverage and datapath coverage.

  • C Based Stimulus for UVM

    This seminar describes a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents. The approach used is to add a C register read/write API for use by C source code, which calls tasks in a SystemVerilog package via the SystemVerilog DPI mechanism to enable the C to make register accesses via the UVM testbench bus agents.

  • Scoreboards and Results Predictors in UVM

    If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case. Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that the DUT properly handles all stimuli it receives. Predictors are components that represent a "golden" model of all or part of the DUT that generate an expected response against which the scoreboard can compare the actual response of the DUT. This online webinar will outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.

  • UVM Debug

    UVM class-based testbenches have become as complex as the designs they are meant to verify, and are, in fact, large object-oriented software designs. As such, new debugging techniques and tools must be employed, beyond the usual RTL debugging techniques that designers have used for years. Through a combination of coding techniques (as documented in the DVCon 2012 2nd Place Best Paper, "Better Living Through Better Class-Based SystemVerilog Debug") and the unique debug facilities in the Questa Verification Platform, this online webinar will show you how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.

  • UVM Connect

    UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment should be using UVM Connect. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment.

  • Introducing UVM Express

    UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. Unfortunately for many teams, UVM's reliance on the object-oriented programming (OOP) features of SystemVerilog and advanced features means that the barrier to adoption of UVM is simply too high. UVM Express makes it easier to adopt key pieces of UVM in a much more straightforward manner, while leaving open the opportunity to adopt full UVM in the future.

  • Customization in UVM

    This recipe will review the configuration database feature of UVM and show you how to organize your testbench to maximize flexibility. You'll be shown how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT. Then we'll cover how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.

  • More UVM Registers

    This recipe will expand on the introductory session delivered in October to discuss how to implement registers and also review score-boarding at the register layer.

  • Introduction to UVM Registers

    The inclusion of the Register Layer was one of the most requested features of UVM. This session will provide an introduction to the Register Layer and show you how to get started writing tests and sequences and checking results at the register layer. We will also show how to use the UVM Register Layer as a standalone package with OVM 2.1.2.

  • Protocol Layering

    Many protocols have a hierarchical definition, and sometimes we may want to create a protocol-independent layer on top of a standard protocol to support the development of protocol-independent components and tests. This session will show how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.

  • OVM to UVM Migration

    A step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.

Learn from the contributing authors of the UVM/OVM Online Cookbook and view all of the recipes.

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New Course: Introduction to the UVM

Join Ray Salemi for the latest course addition to the Verification Academy video library - Introduction to the UVM.

This course will guide you from rudimentary SystemVerilog through a complete UVM testbench

  • Overview and Welcome
  • SystemVerilog Primer for VHDL Engineers
  • SystemVerilog Interfaces
  • Packages, Includes and Macros
  • UVM Components and Tests
  • UVM Environments
  • Connecting Objects
  • Transaction Level Testing
  • The Analysis Layer
  • UVM Reporting
  • Functional Coverage with Covergroups
  • Introduction to Sequences

View the new course.

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