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Mentor Graphics Veloce Emulation Platform Selected by Imagination Technologies for IP Verification Based on Performance and Capacity

WILSONVILLE, Ore.,  April 17, 2014  – Mentor Graphics Corp. (Nasdaq: MENT), a leader in advanced system verification solutions, announced today that Imagination Technologies, a global leader in the supply of semiconductor design IP including PowerVR GPUs and MIPS CPUs, has adopted the Veloce® 2 enterprise emulation platform to complement its existing emulation and verification infrastructure.

“The 800M gate Veloce Maximus helps improve our productivity for verification of our advanced IP cores and the Veloce co-modeling technology enabled us to reduce our regression times,” said Mark Dunn, EVP, IMGworks SoC Design, Imagination Technologies.

“Our collaboration with Imagination has helped drive Veloce to new heights,” said Eric Selosse, vice president of the Mentor Emulation Division. “They’ve shown us how better emulation technology helps their business through benefits such as better coverage of corner cases, increased co-model throughput, better debug, and low power verification. I look forward to continued innovation with this important strategic partner.”

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Mentor Graphics Enterprise Verification Platform Unites Questa and Veloce for 1000x Productivity Gain

WILSONVILLE, Ore.,  April 10, 2014 – Mentor Graphics Corp. (Nasdaq: MENT), today announced the Mentor® Enterprise Verification Platform (EVP), which combines Questa® advanced verification solutions, Veloce® OS3 global emulation resourcing technology, and Visualizer™, a powerful debug environment, into a globally accessible, high-performance datacenter resource. The Mentor EVP features global resource management that supports project teams around the world, maximizing both user productivity and total verification return on investment. The Mentor EVP delivers performance and productivity improvements ranging from 400X to 10,000X.

“Mentor’s verification vision is to deliver an environment where the verification process is completely abstracted from the underlying verification engines from first design thoughts, through silicon, to final product,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics.  “With EVP, Mentor has eliminated the barriers to hardware acceleration and ushered in a new era of enterprise-level verification that combines the functionality and observability of simulation-based verification with the speed of emulation.” 

Mentor® Enterprise Verification Platform (EVP),

Veloce OS3 and Mentor VIP Transform Emulation into a Global, High-Performance Datacenter Resource

To leverage the investment in emulation and allow it to serve as a true enterprise verification resource, emulation must undergo a transformation from project-bound engineering lab instrument to datacenter-hosted global resource.  This transformation begins by eliminating the In-Circuit Emulation (ICE) tangle of cables, speed adaptors and physical devices, replacing them with virtual devices.  The Veloce OS3 VirtuaLAB peripherals are reconfigured instantly to support multiple projects and rapidly shifting priorities.  This is possible because VirtuaLAB is hosted on standard datacenter computers, not proprietary hardware targets.

The OS3 Enterprise Server efficiently manages the global emulation resources, consolidating them to commercial queue managers as a single, high-capacity entity.  The Enterprise Server determines the most efficient location to run each job and immediately serves high-priority jobs by temporarily suspending jobs of lower priority.

Veloce OS3 also delivers advanced verification features to the emulator including PSL/SystemVerilog assertions, functional coverage, and UPF for low power.  This enables a high-performance coverage closure flow and pre-silicon performance analysis of critical SoC subsystems running application software.  To maximize testbench reuse, the Mentor Verification IP, built using standard UVM/RTL, is designed for both simulation and acceleration modes.  These capabilities are in place for a smooth transition from simulation to emulation, allowing for a 1000X performance boost over simulation alone with no loss of functionality.

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Verification Horizons Blog

Verification Knowledge Exchange.
In this BLOG you will find posts from the Verification Academy's Harry Foster, Verification Horizon's Tom Fitzpatrick and Standard's Advocate Dennis Brophy and a host of other Verification Horizon Contributors.

The Verification Horizons Blog will provide an online forum for updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Latest blog post: Mentor Enterprise Verification Platform Debuts by Dennis Brophy

Additional blog posts include:

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Upcoming Verification Events

April 2014:

  • IESF 2014: Military and Aerospace - April 22nd | Dallas, TX - April 24th | Everett, WA - May 1st | Long Beach, CA

    IESF is the global destination for electrical/electronic engineers, managers, and executives in the military and aerospace sectors. For the past 14 years, IESF has been at the forefront of bringing the most brilliant minds together to discuss industry trends, best practices, and product solutions—covering a variety of EE system design disciplines.

    More information and register.

May 2014:

  • Questa Verification IP Workshop - May 6th | Fremont, CA

    This workshop provides an in-depth look at Questa Verification IP (QVIP). QVIP provides a comprehensive test suite, a test plan derived from the protocol specification, assertion-based checks to ensure protocol compliance, and transaction-level debug. QVIP promotes utilization of reusable test bench building blocks, is in compliance with industry standards and protocols, and is ready to deploy in verification environments employing advanced methodologies such as UVM.

    More information and register.

  • Step-up Your Verification Efficiency - May 7th | Kista, Sweden

    In this seminar we will provide perspectives into the market forces that are driving FPGA development environments, show you a common and practical example of an improved verification process and show you the resources to deploy. You can effectively break the FPGA design verification barrier.

    More information and register.

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Mentor Graphics Announces the Questa X-Value Verification Solution

WILSONVILLE, Ore., April 1, 2014 — Mentor Graphics Corp. (NASDAQ: MENT), today announced availability of a new solution for X-value verification in register transfer level (RTL) and gate level designs. X-values are symbols that represent unknown voltage levels of signals in digital IC designs. The latest version of the Questa® Verification Platform links simulation and formal verification capabilities to deliver complete X-value analysis and debug, which helps an IC design team avoid the risk of silicon and simulation failure. These new capabilities target both of the problematic effects of X-values that can lead to silicon bugs and wasted design effort: X-optimism and X-pessimism. 

“Even though awareness of X issues is good, and designers do their best to follow coding guidelines to avoid X-state bugs, we still face the challenge of eliminating all X-related silicon bugs with traditional verification methods,” said Meng-Han Hsieh, director of Design Platform Division, MediaTek Inc. “The Questa X-value verification solution has proven to be of immense value in catching X bugs which would have been difficult to detect otherwise.”

“Within the Questa Platform we combine formal and simulation to obtain results that couldn’t be achieved with either of these technologies used independently,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “The X-value verification solution brings these complementary technologies together to help our customers overcome the risks of silicon and simulation failures caused by X-states.”

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Basic UVM & UVM Express Courses, now available as Japanese PDFs

The Verification Academy is now offering 2 UVM Courses as Japanese translated PDFs.

Basic UVM

UVM Express

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DVCon 2014 Featured Presentations

The following papers were presented at DVCon 2014.

Of Camels and Committees - Standards Should Enable Innovation, Not Strangle It

Presentation Slides by Tom Fitzpatrick and Dave Rich, Mentor Graphics Corporation

UVM SchmooVM – I Want My C Tests! (2014 Best Poster Paper)

by Rich Edelman and Raghu Ardeishar, Mentor Graphics Corporation

Wiretap your SoC - Why scattering Verification IPs throughout your design is a smart thing to do

Presentation Slides by Avidan Efody, Mentor Graphics Corporation

Tried/Tested speedups for SW-driven SoC Simulation

Presentation Slides by Gordon Allan, Mentor Graphics Corporation

Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and Debug

by Rich Edelman and Raghu Ardeishar, Mentor Graphics Corporation

Tackling Random Blind Spots with Strategy-Driven Stimulus Generation

by Matthew Ballance, Mentor Graphics Corporation

Bringing Regression Systems into the 21st Century

by David Crutchfield, Cypress Semiconductor, Thom Ellis, Mentor Graphics Corporation

Are you really confident that you are getting the very best from your verification resources?

by Fritz Ferstl, Univa, Darron May, Mentor Graphics Corporation

Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology (2014 Poster Honorable Mention)

by Gaurav Kumar Verma and Doug Warmke, Mentor Graphics Corporation

So you think you have good stimulus: System-level distributed metrics analysis and results

by Alan Hunder, ARM, Andreas Meyer, Mentor Graphics Corporation

Stepping into UPF 2.1 world: Easy solution to complex Power Aware Verification

Presentation Slides by Amit Srivastava and Madhur Bhargava, Mentor Graphics Corporation

Is your Power Aware design really x-aware?

by Durgesh Prasad and Jitesh Bansal, Mentor Graphics Corporation

Using Test-IP Based Verification Techniques in a UVM Environment

by Vidya Bellippady and Sundar Haran, Microsemi Corporation, Jay O'Donnell, Mentor Graphics Corporation

Interpreting UPF for a Mixed-Signal Design Under Test

Presentation Slides by Kenneth Bakalar and Eric Jeandeau, Mentor Graphics Corporation

Equivalence Validation of Analog Behavioral Models

by Hardik Parekh, Manish Kumar Karna, Mohit Jain, ST Microelectronics PVT, LTD., Atul Pandey and Sandeep Mittal, Mentor Graphics Corporation

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Mentor Graphics Proposes New Accellera Standards Committee for Graph-Based Test Specification Standard

WILSONVILLE, Ore., March 4, 2014 - Mentor Graphics Corp. (NASDAQ: MENT), today announced it has proposed that a new Accellera standards committee be formed to investigate the standardization of a graph-based test specification standard. To underscore this endeavor, Mentor will make a technical donation of its existing graph-based test specification format to jump-start the standardization effort.

“The Mentor graph-based specification technology brings compelling new value to the verification domain with its capabilities for quickly and exhaustively covering the device state space,” said Peter Jensen, owner and managing director, SyoSil. “This lets us use a unified graph-based description for traditional coverage-driven verification using UVM at the block level, as well as intelligent software-driven verification using embedded C test programs at the system level.” 

“Having access to the most advanced functional verification methodologies is essential to maximize electronic design and verification efficiency, and we have seen customers realize a ten-fold gain in productivity through the adoption of graph-based test technology,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “Based on customer feedback, we’re moving forward to recommend and facilitate a standards effort that brings significant benefits to a large number of users, and opens the door to technology innovation.”

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Verification Horizons - March 2014 Issue

Volume 10, Issue 1.
Now available, the latest issue of Verification Horizons.

Access the articles below and the complete issue.

Verification Horizons March 2014 articles include:

  • Whether It's Fixing a Boiler, or Getting to Tapeout, It's Productivity that Matters
  • Don't Forget the Little Things That Can Make Verification Easier
  • Taming Power Aware Bugs with Questa®
  • Using Mentor Questa® for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments
  • Dealing With UVM and OVM Sequences
  • Stories of an AMS Verification Dude: Putting Stuff Together
  • Portable VHDL Testbench Automation with Intelligent Testbench Automation

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Verification Cookbook Seminars

Web Seminar Series featuring the Verification Methodology Cookbook.

The Verification Methodology Cookbook is an encyclopedia of Verification Methodology and is utilized by Verification Engineers across the globe to stay current with UVM, OVM and Coverage.

This series of online seminars, will focus on a featured monthly "recipe" guiding users into a deeper understanding of the material.

Web seminar recipes include:

  • Raising Productivity Using Abstract UVM Stimulus and Intelligent Automation

    The benefits that UVM provides in specifying modular reusable testbenches have been well documented. Regardless of these benefits, however, the need to adequately model functional coverage, and efficiently create stimuli to reach your coverage goals, remains. The use of UVM sequences allows encapsulation of constrained-random stimulus that can be reused, and virtual sequences allow composition to orchestrate stimuli on multiple interfaces to your DUT.

    This web seminar will introduce you to abstract stimulus specification to provide more effective UVM tests that can be reused throughout your SoC flow and show you how Questa employs intelligent automation to achieve coverage closure faster.

  • Automating the Creation of Your UVM Register Model

    The UVM Register Layer is a great way to abstract the interaction between your testbench and your DUT from the pin-level, or even protocol-specific transactions to a generic register-based view of communication. This abstraction provides many benefits, not the least of which is isolating your stimulus generation and coverage modeling from low-level changes in your design (i.e. separating the what from the how). Unfortunately, the benefits of using the register layer come at the cost of having to specify the register models in your testbench to reflect the registers in your hardware. With thousands or even tens of thousands of registers in a typical design, this can be a laborious and error-prone process when done from scratch. This UVM Recipe of the Month will introduce the Register Assistant feature of the Questa Verification Platform and show how it can be used to quickly generate correct-by-construction register models and tests from a register specification.

  • Advanced UVM Debug

    The use of UVM and SystemVerilog to create object-oriented testbenches has magnified the need for a good debugging solution to allow engineers to focus on verifying the design, not fixing problems in the testbench. This web seminar will highlight some new strategies for debugging UVM-based testbenches.

  • Beyond UVM: Effectively Modeling and Analyzing Coverage

    This archived web seminar will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage, and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret. From there, we will review several examples that illustrate effective functional coverage for various applications, including bus protocol coverage, register-based block-level coverage and datapath coverage.

  • C Based Stimulus for UVM

    This seminar describes a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents. The approach used is to add a C register read/write API for use by C source code, which calls tasks in a SystemVerilog package via the SystemVerilog DPI mechanism to enable the C to make register accesses via the UVM testbench bus agents.

  • Scoreboards and Results Predictors in UVM

    If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case. Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that the DUT properly handles all stimuli it receives. Predictors are components that represent a "golden" model of all or part of the DUT that generate an expected response against which the scoreboard can compare the actual response of the DUT. This online webinar will outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.

  • UVM Debug

    UVM class-based testbenches have become as complex as the designs they are meant to verify, and are, in fact, large object-oriented software designs. As such, new debugging techniques and tools must be employed, beyond the usual RTL debugging techniques that designers have used for years. Through a combination of coding techniques (as documented in the DVCon 2012 2nd Place Best Paper, "Better Living Through Better Class-Based SystemVerilog Debug") and the unique debug facilities in the Questa Verification Platform, this online webinar will show you how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.

  • UVM Connect

    UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment should be using UVM Connect. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment.

  • Introducing UVM Express

    UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. Unfortunately for many teams, UVM's reliance on the object-oriented programming (OOP) features of SystemVerilog and advanced features means that the barrier to adoption of UVM is simply too high. UVM Express makes it easier to adopt key pieces of UVM in a much more straightforward manner, while leaving open the opportunity to adopt full UVM in the future.

  • Customization in UVM

    This recipe will review the configuration database feature of UVM and show you how to organize your testbench to maximize flexibility. You'll be shown how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT. Then we'll cover how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.

  • More UVM Registers

    This recipe will expand on the introductory session delivered in October to discuss how to implement registers and also review score-boarding at the register layer.

  • Introduction to UVM Registers

    The inclusion of the Register Layer was one of the most requested features of UVM. This session will provide an introduction to the Register Layer and show you how to get started writing tests and sequences and checking results at the register layer. We will also show how to use the UVM Register Layer as a standalone package with OVM 2.1.2.

  • Protocol Layering

    Many protocols have a hierarchical definition, and sometimes we may want to create a protocol-independent layer on top of a standard protocol to support the development of protocol-independent components and tests. This session will show how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.

  • OVM to UVM Migration

    A step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.

Learn from the contributing authors of the UVM/OVM Online Cookbook and view all of the recipes.

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