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Verification Horizons - November 2018 Issue

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Verification Horizons Blog

Verification Knowledge Exchange.
In this BLOG you will find posts from the Verification Academy's Harry Foster, Verification Horizon's Tom Fitzpatrick and Standard's Advocate Dennis Brophy and a host of other Verification Horizon Contributors.

The Verification Horizons Blog will provide an online forum for updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Latest blog post: Latest Verification Horizons Newsletter Is Now Available - Tom Fitzpatrick

Additional blog posts include:

Part 3 – FPGA Verification Effort Trends: The 2018 Wilson Research Group Functional Verification Study - Harry Foster
Part 2 – FPGA Verification Effectiveness: The 2018 Wilson Research Group Functional Verification Study - Harry Foster
Part 1 – FPGA Design Trends: The 2018 Wilson Research Group Functional Verification Study - Harry Foster
Understanding and Minimizing Study Bias (2018 Study): The 2018 Wilson Research Group Functional Verification Study - Harry Foster
Prologue: The 2018 Wilson Research Group Functional Verification Study - Harry Foster
How to Reduce the Complexity of Formal Analysis | Part 6 – Leveraging Data Independence and Non-Determinism - Joe Hupcey III
Accellera Day India 2018 - Dennis Brophy
How to Reduce the Complexity of Formal Analysis | Part 5 – Memory Abstraction - Joe Hupcey III
Adding Functional Safety to Verification Academy - Tom Fitzpatrick
How to Prove that It’s Not Your Fault - Tom Fitzpatrick
Emerging Commercial Acceptance of RISC-V - Dennis Brophy
Upcoming Wilson Research Group Functional Verification Study Web Seminar - Harry Foster
Counter Abstraction - Joe Hupcey III
Assertion Decomposition - Joe Hupcey III
Prospecting for Reusable Assets with Portable Stimulus - Matthew Ballance

Boosts verification productivity by up to 5X with nanometer-scale SPICE accuracy, advanced debug capabilities and best-in-class usability
Allows users to remain in existing use model and maximize reuse of verification infrastructure

Mentor, a Siemens business, today announced the availability of the Symphony Mixed-Signal Platform, which combines the leading foundry-certified Analog FastSPICE (AFS™) circuit simulator with industry-standard HDL simulators to provide fast and accurate verification of complex nanometer-scale mixed-signal integrated circuits (ICs). Offering an intuitive use model and complete reusability of existing verification infrastructure, Symphony delivers up to 5X productivity improvements in mixed-signal verification over traditional flows.

Systems on Chips (SoCs) used in high-performance computing, Internet of Things (IoT) and automotive applications have multiple high-performance, low-noise mixed-signal interfaces. A versatile mixed-signal verification platform is needed to help designers verify connectivity, functionality and performance across mixed-signal circuitry on the chip, which in turn drives a very large number of mixed-signal simulations at the block and top levels. Mixed-signal simulation solutions must be fast, accurate, easy to use and seamlessly integrated into existing analog and digital verification flows to meet time-to-market requirements.

Underscoring Siemens’ continued commitment to invest for EDA leadership, Mentor’s Symphony Platform is built from the ground up to solve these complex mixed-signal verification challenges. Symphony’s modular architecture leverages Mentor’s AFS circuit simulator to provide exceptionally fast mixed-signal simulation performance with nanometer-scale SPICE accuracy and compatibility with all leading digital solvers, including Mentor’s Questa® functional verification tool family.

“IDT is standardizing on Symphony because our timing products require high accuracy verification for high-speed phase-locked loops that combine digital calibration blocks with analog functionality,” said Brian Buell, design director at IDT. “Using Mentor’s Symphony Mixed-Signal Platform, we are able to efficiently run several test benches to validate the digital calibration of our phase-locked loops with 3X performance improvement over our previous solution. Symphony has significantly improved our verification productivity through its intuitive setup, use model and excellent debugging capabilities.”

Symphony allows users to remain in their existing use model and maximize reuse of their existing verification infrastructure, including test benches, encrypted IP blocks, and digital/analog netlists. Symphony’s accuracy, performance and intuitive use model, coupled with powerful debugging capabilities and extensive boundary element and configuration support, enable a broad range of verification capabilities including connectivity and functionality checks, as well as mixed-signal IP characterization across A/D subsystems.

“To ensure first-time, full-specification compliance of our touch and proximity sensor ICs, we need to run full-chip simulations with high accuracy. Running these simulations at transistor level is prohibitively slow with unacceptable turnaround times in the range of several days,” said Rémi Le Révérend, design director for Sensing Solutions group at Semtech, a leading IC provider for touch and proximity sensing applications. “Using Mentor’s Symphony Mixed-Signal Platform, we were able to complete these simulations in a few hours with the same results as the full transistor-level simulations. Symphony’s simple use model and the ability to plug seamlessly into our verification flow boosted our productivity significantly. We will continue to address our verification challenges with Symphony.”

“Our customers require significant productivity improvements to their existing mixed-signal verification flows,” said Ravi Subramanian, general manager and vice president of Mentor’s IC Verification Solutions. “With Symphony, we are proud to deliver another key capability for our analog/mixed-signal verification portfolio that enables our customers to access high-performance nanometer-scale, SPICE-accurate mixed-signal verification capabilities in a simple and compelling use-model that will enable them to deliver superior products to market significantly faster.”

For more information about the Symphony Mixed-Signal Platform, please visit http://go.mentor.com/53HNe or contact your local Mentor account representative.

Mentor’s Questa verification solution helps Leonardo accelerate aerospace FPGA development

Mentor, a Siemens business, announced today that Leonardo has accelerated its field programmable gate array (FPGA) design cycle, using advanced verification techniques made possible with the Questa™ verification solution.

Leonardo is among the top ten global players in Aerospace, Defense and Security. Mentor’s Questa provides a comprehensive, best-in-industry verification solution for integrated circuit (IC) design and verification.

Leonardo has been using Mentor’s Questa SystemVerilog verification solution, applying the Universal Verification Methodology (UVM) framework and Questa Verification IP (QVIP) to the design, verification and validation (V&V) of highly complex avionics interfaces. Results achieved to date indicate an acceleration of the design, V&V and system integration phases of a key product.

Incorporation of the UVM framework, QVIP and Verification Run Manager into a Jenkins software-based environment has extracted further value from the toolkit, enabling automated reverification of designs, post modification.

Electronically scanned array radar systems contain a multitude of central processing units (CPUs) and FPGAs, spread across several subsystems, with the FPGAs implementing control, digital signal processing (DSP) and communication functions. “Designing a complex system like this is a daunting task, especially when you take into account the tight schedule demanded by today’s fast-paced marketplace,” said Iain Wildgoose, vice president of Engineering, Radar and Advanced Targeting for Leonardo’s Airborne and Space Systems Division. “The reuse and scalability that the UVM framework and QVIP delivered, combined with the support to the adoption process provided by Mentor consultants and application engineers, were key enablers to successful design and integration.”

Mentor QVIP provides an easy-to-use library of verification IP for more than 40 standard protocols and 1,700 memory devices. QVIP includes checkers and coverage, plus a comprehensive set of stimulus sequences for the protocols. Adoption of QVIP IP for the standard interfaces enabled Leonardo to focus on the unique specifics of the company’s design. QVIP and the UVM framework — a set of base classes layered on top of UVM — have enabled Leonardo to increase code coverage significantly in a short period of time.

Live Events

UVM Framework - Web Seminar | 8:30 AM US/Pacific | December 20th
Advance Your Verification Methodology - Seminar | January 17th | El Segundo, CA

Verification Horizons - June 2018 Issue

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Mentor’s next-generation Questa inFact to fully support Accellera’s Portable Test and Stimulus Standard 1.0

Mentor, a Siemens business, which pioneered portable stimulus technology in 2004, announced it will fully support the new Accellera Portable Test and Stimulus Standard 1.0 in the upcoming release of its Questa® inFact™ tool. The Accellera standard, which is based on Questa inFact technology that Mentor donated to Accellera in 2014, will rapidly drive portable stimulus into broader, mainstream use and help IC engineers more efficiently collaborate and deliver innovation to markets such as artificial intelligence, 5G wireless communication and autonomous driving.

At its core, the new Accellera portable stimulus standard (PSS) enables engineers to re-use a single set of portable stimulus specifications across multiple verification engines to achieve different objectives at various stages of the development process. Mentor’s Questa inFact tool is the industry’s most comprehensive solution, supporting design, verification, validation and test. It leverages machine learning and data mining techniques that have yielded up to a 40X increase in productivity across multiple phases of customer IC development. The Questa InFact tool leverages portable stimulus technology, enabling designers to complete advanced performance and power analysis at the IC level, verification engineers to achieve higher levels of coverage in less time, validation engineers to fully integrate hardware and software, and test engineers to analyze and optimize their regression test environments.

“When Mentor donated the Questa inFact tool’s language and initiated the original Accellera Portable Test and Stimulus Working Group in 2014, we did so to drive portable stimulus toward mainstream use and help more design teams realize the step-function gains in verification productivity afforded by our Questa inFact tool,” said Mark Olen, product marketing group manager for the Mentor IC Verification Solutions Division. “As we’ve collaborated with Accellera’s PSS working group to drive the specification to this standard over the last four years, we’ve also been diligently refining Questa inFact to comply with the portable specification as it has evolved. We have additionally added the latest machine learning and data mining technologies to expand the Questa inFact tool’s use for the design, validation and regression test phases of the IC development process.”

Customers use the Questa inFact tool to generate UVM SystemVerilog test scenarios to achieve functional coverage at the IP block level with the Questa simulator, and then re-use the test scenarios to generate C/C++ tests for traffic generation at IC level verification with the Veloce® emulator. Customers also use the Questa inFact tool to generate assembly code at the system level for instruction-set verification. In addition, the tool can generate C/C++ scenarios for architectural exploration with the Vista™ virtual prototyping system. Lastly, customers use the Questa inFact tool in concert with Mentor’s Catapult® High-Level Synthesis toolset by generating C/C++ scenarios before, and RTL tests after, behavioral synthesis.

Mentor has applied classification machine learning to its graph-based Questa inFact technology to enable the actual targeting of scenarios not yet verified. This enables much faster achievement of coverage goals at the IP block level, and increased usefulness of bare metal testing at the IC level. Mentor’s Questa inFact tool learns from each subsequent scenario during simulation or emulation -- the longer it runs, the smarter it gets.

Mentor has also applied data mining technology to extend the application of portable stimulus beyond verification. The Questa inFact tool can collect and correlate transaction-level activity to characterize IC design performance parameters including fabric routing efficiency and bandwidth, system-level latency, cache coherency, arbitration efficiency, out-of-order execution, and even opcode performance. It can also analyze and optimize regression test environments, eliminating costly and redundant simulation and emulation cycles.

“We have been using early versions of this standard in Mentor’s Questa inFact tool for many years to help customers leverage PSS to achieve their design goals,” said Srini Venkataramanan, chief technology officer for Contemporary Verification Consultants, Ltd. (CVC). “With the new Accellera standard in place, we believe adoption will accelerate and we will be able to help customers achieve even greater success."

The Veloce Strato platform offers data center options: hardware emulation on-premises, off-premises and on Amazon Web Services

Mentor, a Siemens business, today announced that the Veloce® Strato platform is now a customer-validated cloud computing emulation platform directly accessible on-demand on Amazon Web Services (AWS). This new data center use model extends the availability of hardware emulation across a broad range of deployment scenarios to ensure that all semiconductor companies have access to hardware emulation for system-on-chip (SoC) and system-of-systems verification.

As the need for hardware emulation changes within a company, there are now more options for deployment of emulation solutions in a data center. Many customers choose to deploy their emulation resources in an on-premise strategy, while others choose an off-premise or co-located strategy based on business needs. Now there is another distinct option, as Mentor has worked in collaboration with AWS to enable access to the Veloce platform directly from AWS. This important milestone reinforces Mentor’s strong commitment to providing its semiconductor customers with a full complement of services on the cloud for end-to-end semiconductor design and verification.

New Veloce StratoT footprint demonstrates the scalability of the Veloce Strato platform while delivering best total cost of ownership
Building on strong marketplace acceptance of the Veloce Strato platform, new Veloce StratoT offers customers additional configuration options

Mentor, a Siemens business, today introduced the Veloce® StratoT, which expands the footprint choices and configuration options available from its Veloce Strato™ emulation platform family. The Veloce Strato platform is a third-generation, data-center friendly emulation platform, and the only emulation platform on the market with full scalability across both software and hardware. In addition, the Veloce Strato platform is the first emulation platform in the industry to establish a roadmap to 15 billion gate capacity.

The Veloce StratoT features a unique footprint that expands capacity options and demonstrates continuity in the capacity roadmap for the Veloce Strato platform. The Veloce StratoT supports designs from 40 million gates (MG) up to 1.25 billion gates (BG) depending on configuration, features power consumption of 17kW, and represents an ideal solution for data center applications. A fully loaded Veloce StratoT supports up to 32 independent users, and delivers the best power-per-gate on the market. With the expansion of the Veloce Strato platform, customers now have a secure roadmap for significantly increasing emulation capacity within the same hardware family, while protecting their initial investment and achieving best cost of ownership.

“What we appreciate most is that the Veloce Strato roadmap not only addresses growing capacity needs, but it also maps to the diverse and expanding challenges of HW/SW validation,” said Nasr Ullah, senior director of Samsung Electronics PowerPerformance architecture team, SARC (Samsung Austin Research Center). “With the Veloce Strato emulation platform we get more than just talk about ‘shift left’, we get technology that makes the shift left promise a reality in a way that can be easily executed in our existing verification environment.”

“Since its introduction in February 2017, the Veloce Strato platform has earned rave reviews from customers across a wide range of applications,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “Customers like the scalability of the Veloce Strato platform, and now the new Veloce StratoT gives them even more options relative to capacity and footprint. Based on customer feedback, there is clear indication that the Veloce Strato platform represents a roadmap capable of successfully serving the emulation market for the years to come.”

About the Veloce Strato emulation platform

The Veloce Strato emulation platform uses innovative software running on powerful, qualified hardware and an extensible operating system, to target design risks faster than hardware-centric strategies. Now considered among the most versatile and powerful of verification tools, emulation greatly expands the ability of project teams to conduct hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation and performance characterization. The Veloce Strato platform further reinforces Mentor’s role as an industry pioneer in all facets of hardware emulation, with the largest portfolio of use models (Apps), best total throughput, fastest co-model bandwidth and time-to-visibility, and plans for highest effective capacity available.

Mentor delivers the most comprehensive Enterprise Verification Platform™ (EVP), delivering performance and productivity improvements ranging from 400X to 10,000X. Tightly integrated combining Questa® for high performance simulation, verification management and coverage closure, low-power, CDC & Formal Verification, Veloce® for hardware emulation and HW/SW system verification, Catapult® for High-Level Synthesis, PowerPro® for RTL Low-Power unified with the Visualizer™ debug environment. The following papers, posters and tutorials, were featured at DVCon 2018. Need to become a member?

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