Complex testing and methodology with complex silicon requires powerful but simple to use debug solutions. In this 3-part web seminar series, Debug Expert, Rich Edelman will explore better UVM debugging, debug for Verilog and debug for VHDL including automation for driver tracing and X-tracing, post-simulation and live-simulation debug, class based debug and transaction debug.
The Visualizer Debug Environment is a powerful framework for debug and verification for simulation, emulation, formal, CDC, lint, analog and other technologies. Assertion debug and coverage analysis are available, along with traditional waveform debug, source code debug with the capacity and performance for even large gate-level designs.
Session Details:
Better UVM Debug with Visualizer
- Tuesday, June 2nd
- 8:00 AM-9:00 AM US/Pacific
Introduction to Visualizer for the Verilog Users
- Tuesday, June 16th
- 8:00 AM-9:00 AM US/Pacific
Introduction to Visualizer for the VHDL Users
- Tuesday, June 30th
- 8:00 AM-9:00 AM US/Pacific
