Search form

Main menu

My Account Menu

Academy News

Subscribe to Academy News

Mentor Graphics Proposes New Accellera Standards Committee for Graph-Based Test Specification Standard

WILSONVILLE, Ore., March 4, 2014 - Mentor Graphics Corp. (NASDAQ: MENT), today announced it has proposed that a new Accellera standards committee be formed to investigate the standardization of a graph-based test specification standard. To underscore this endeavor, Mentor will make a technical donation of its existing graph-based test specification format to jump-start the standardization effort.

“The Mentor graph-based specification technology brings compelling new value to the verification domain with its capabilities for quickly and exhaustively covering the device state space,” said Peter Jensen, owner and managing director, SyoSil. “This lets us use a unified graph-based description for traditional coverage-driven verification using UVM at the block level, as well as intelligent software-driven verification using embedded C test programs at the system level.” 

“Having access to the most advanced functional verification methodologies is essential to maximize electronic design and verification efficiency, and we have seen customers realize a ten-fold gain in productivity through the adoption of graph-based test technology,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “Based on customer feedback, we’re moving forward to recommend and facilitate a standards effort that brings significant benefits to a large number of users, and opens the door to technology innovation.”

Read more →

Verification Horizons Blog

Verification Knowledge Exchange.
In this BLOG you will find posts from the Verification Academy's Harry Foster, Verification Horizon's Tom Fitzpatrick and Standard's Advocate Dennis Brophy and a host of other Verification Horizon Contributors.

The Verification Horizons Blog will provide an online forum for updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Latest blog post: DVCon 2014 Issue of Verification Horizons Now Available by Tom Fitzpatrick

Additional blog posts include:

Read more →

Verification Horizons - March 2014 Issue

Volume 10, Issue 1.
Now available, the latest issue of Verification Horizons.

Access the articles below and the complete issue.

Verification Horizons March 2014 articles include:

  • Whether It's Fixing a Boiler, or Getting to Tapeout, It's Productivity that Matters
  • Don't Forget the Little Things That Can Make Verification Easier
  • Taming Power Aware Bugs with Questa®
  • Using Mentor Questa® for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments
  • Dealing With UVM and OVM Sequences
  • Stories of an AMS Verification Dude: Putting Stuff Together
  • Portable VHDL Testbench Automation with Intelligent Testbench Automation

Read more →

Upcoming Verification Events

March 2014:

  • DVCon 2014 - March 3rd - 6th | San Jose, CA

    Mentor Graphics delivers the most comprehensive and unified advanced verification portfolio available: including Questa® for high performance simulation and debug, verification management and coverage closure, low-power verification with UPF, CDC, Formal Verification, accelerated functional coverage, processor-based hardware verification and Veloce® for high-performance system verification.

    More information and register.

  • Injecting Automation into Verification - FPGA Market Trends - March 18th | 8:00 AM - 9:00 AM US/Pacific

    This webinar is a manager's introduction to trends in the FPGA market and provide a business perspective on how companies are crossing the FGPA design verification barrier. Learn the common tools, techniques and learning aids that make an effective FPGA verification process. We will discuss the business and technical merits of common techniques and processes that your team can start deploying now. This series has three main concepts, coverage metrics, assertions for debug, and verification throughput. Each of the three concepts can be adopted incrementally or entirely and are offered as separate technical webinars.

    More information and register.

  • Injecting Automation into Verification - Code Coverage - March 20th | 8:00 AM - 9:00 AM US/Pacific

    Code Coverage is a method used to determine the effectiveness of the testbench for a piece of HDL code, which it does by measuring and indicating what percentage of the design was exercised by this testbench. The concept originally came from the software world where this is used in almost every software development organisation in their verification cycles. Despite the similarity of HDL code to software written in languages such as C, it is not so extensively used in HDL code verification.

    More information and register.

  • Injecting Automation into Verification - Assertions - March 25th | 8:00 AM - 9:00 AM US/Pacific

    Assertions have proven value in identifying bugs where and when they occur. This is one dimension of improving debug throughput. This webinar will show how you can leverage Assertions, including the pre-defined, pre-tested OVL libraries. Automation is an essential component in adoption of technology; we will highlight our Assertion Manager. The Assertion Manager will help you identify and create pre-configured checkers so that you can improve your debug productivity associated with Assertions, as the monitoring of the Assertions is done fully automatically by the simulator. This further reduces the load of the engineer during verification and regression.

    More information and register.

  • Mentor Forum - March 25th | Tel Aviv, Israel

    Mentor Forum Israel brings together engineers and managers coming from all electronics companies in Israel. We've packed the day full of exciting activities focused on the latest in cutting-edge design. Choose from numerous presentations, including keynotes and breakout tracks on topics addressing the following domains: IC design and test, physical verification, SoC verification, functional verification and PCB systems.

    More information and register.

  • Injecting Automation into Verification - Improved Throughput - March 27th | 8:00 AM - 9:00 AM US/Pacific

    This webinar will focus on the highest value tools and techniques for improving test stimulus, debug effectiveness and simulation throughput. One of the most common verification process improvement opportunities is being able to more easily create test cases, including leveraging standard bus interfaces like PCIe for stimulating your system. We will also describe common techniques for improving simulation performance. If you are able to stimulate your design with simulation more effectively you will find that debug productivity in simulation is vastly superior to debug time in an hardware lab. We will show common and recent improvements in simulation debug throughput. We also highlight additional pre-built verification automation components for verification process throughput.

    More information and register.

Read more →

Verification Cookbook Seminars

Web Seminar Series featuring the Verification Methodology Cookbook.

The Verification Methodology Cookbook is an encyclopedia of Verification Methodology and is utilized by Verification Engineers across the globe to stay current with UVM, OVM and Coverage.

This series of online seminars, will focus on a featured monthly "recipe" guiding users into a deeper understanding of the material.

Web seminar recipes include:

  • Raising Productivity Using Abstract UVM Stimulus and Intelligent Automation

    The benefits that UVM provides in specifying modular reusable testbenches have been well documented. Regardless of these benefits, however, the need to adequately model functional coverage, and efficiently create stimuli to reach your coverage goals, remains. The use of UVM sequences allows encapsulation of constrained-random stimulus that can be reused, and virtual sequences allow composition to orchestrate stimuli on multiple interfaces to your DUT.

    This web seminar will introduce you to abstract stimulus specification to provide more effective UVM tests that can be reused throughout your SoC flow and show you how Questa employs intelligent automation to achieve coverage closure faster.

  • Automating the Creation of Your UVM Register Model

    The UVM Register Layer is a great way to abstract the interaction between your testbench and your DUT from the pin-level, or even protocol-specific transactions to a generic register-based view of communication. This abstraction provides many benefits, not the least of which is isolating your stimulus generation and coverage modeling from low-level changes in your design (i.e. separating the what from the how). Unfortunately, the benefits of using the register layer come at the cost of having to specify the register models in your testbench to reflect the registers in your hardware. With thousands or even tens of thousands of registers in a typical design, this can be a laborious and error-prone process when done from scratch. This UVM Recipe of the Month will introduce the Register Assistant feature of the Questa Verification Platform and show how it can be used to quickly generate correct-by-construction register models and tests from a register specification.

  • Advanced UVM Debug

    The use of UVM and SystemVerilog to create object-oriented testbenches has magnified the need for a good debugging solution to allow engineers to focus on verifying the design, not fixing problems in the testbench. This web seminar will highlight some new strategies for debugging UVM-based testbenches.

  • Beyond UVM: Effectively Modeling and Analyzing Coverage

    This archived web seminar will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage, and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret. From there, we will review several examples that illustrate effective functional coverage for various applications, including bus protocol coverage, register-based block-level coverage and datapath coverage.

  • C Based Stimulus for UVM

    This seminar describes a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents. The approach used is to add a C register read/write API for use by C source code, which calls tasks in a SystemVerilog package via the SystemVerilog DPI mechanism to enable the C to make register accesses via the UVM testbench bus agents.

  • Scoreboards and Results Predictors in UVM

    If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case. Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that the DUT properly handles all stimuli it receives. Predictors are components that represent a "golden" model of all or part of the DUT that generate an expected response against which the scoreboard can compare the actual response of the DUT. This online webinar will outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.

  • UVM Debug

    UVM class-based testbenches have become as complex as the designs they are meant to verify, and are, in fact, large object-oriented software designs. As such, new debugging techniques and tools must be employed, beyond the usual RTL debugging techniques that designers have used for years. Through a combination of coding techniques (as documented in the DVCon 2012 2nd Place Best Paper, "Better Living Through Better Class-Based SystemVerilog Debug") and the unique debug facilities in the Questa Verification Platform, this online webinar will show you how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.

  • UVM Connect

    UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment should be using UVM Connect. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment.

  • Introducing UVM Express

    UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. Unfortunately for many teams, UVM's reliance on the object-oriented programming (OOP) features of SystemVerilog and advanced features means that the barrier to adoption of UVM is simply too high. UVM Express makes it easier to adopt key pieces of UVM in a much more straightforward manner, while leaving open the opportunity to adopt full UVM in the future.

  • Customization in UVM

    This recipe will review the configuration database feature of UVM and show you how to organize your testbench to maximize flexibility. You'll be shown how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT. Then we'll cover how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.

  • More UVM Registers

    This recipe will expand on the introductory session delivered in October to discuss how to implement registers and also review score-boarding at the register layer.

  • Introduction to UVM Registers

    The inclusion of the Register Layer was one of the most requested features of UVM. This session will provide an introduction to the Register Layer and show you how to get started writing tests and sequences and checking results at the register layer. We will also show how to use the UVM Register Layer as a standalone package with OVM 2.1.2.

  • Protocol Layering

    Many protocols have a hierarchical definition, and sometimes we may want to create a protocol-independent layer on top of a standard protocol to support the development of protocol-independent components and tests. This session will show how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.

  • OVM to UVM Migration

    A step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.

Learn from the contributing authors of the UVM/OVM Online Cookbook and view all of the recipes.

Read more →

Academy Survey

We want to hear from you!

In an effort to continue to fulfill your online learning needs today, and into the future, we ask that you login to your Verification Academy Full Access account and take a few minutes to fill out a survey.

Those whom complete the survey will become eligible to win an Amazon Gift Card (1 of 3), a $100 value.

Please respond by Friday, January 24th.

Access the survey.

Read more →

Advanced UVM Course Updated

Join Tom Fitzpatrick for the latest updated course - Advanced UVM.

All ten sessions have been updated!

  • Architecting a UVM Testbench
  • Understanding the Factory and Configuration
  • How TLM Works
  • Modeling Transactions
  • The Proper Care and Feeding of Sequences
  • Layered Sequences
  • Writing and Managing Tests
  • Setting Up the Register Layer
  • Using the Register Layer
  • Register-Based Testing

View the updated course.

Read more →

Verification Academy Forum Update

We are excited to announce that the Verification Academy has released a major Forum update. We've taken your feedback and have integrated a number of enhancements and feature requests.

Please take a few moments and review the Forum FAQ.

Read more →

Mentor Graphics Questa Platform Chosen for DMP Reference Verification Flow

WILSONVILLE, Ore., Nov. 19, 2013—Mentor Graphics Corp. (NASDAQ: MENT), today announced that Digital Media Professionals (DMP) has qualified the Questa® functional verification platform for use on its advanced graphics IP that implements DMP's advanced algorithms. DMP also uses the Questa functional verification platform on its portfolio of 3D and 2D graphics system-on-chip (SoC) solutions to meet the diverse needs of customers such as performance, function, gate size and cost.

DMP is recognized as the leading IP supplier in the embedded graphics device market with its high performance algorithm to bring stunning results for both 2D vector and 3D graphics. The company’s solutions are widely adopted in mobile, home, amusement, car and many more electronic product application areas.

The Questa functional verification platform was chosen because it provides a full complement of verification capabilities, from planning to testbench implementation and results analysis, all tuned to extract the most value and efficiency from the Universal Verification Methodology (UVM), the industry standard functional verification methodology, which DMP uses for its verification infrastructure.

An example of this tuning is DMP’s use of the Questa platform in a specification-driven flow to create correct-by-construction register models automatically for their verification environment. The UVM register package was created to support verification of complex IP and SoCs, which employ large numbers of registers, but modeling the registers for verification by hand is a labor-intensive and error-prone process. Using the Questa platform, DMP engineers can simply import register definitions from a spreadsheet or other specification and instantly create their register verification models, as well as automated tests for the entire register set.

“Customers using our graphics IP are facing intense competition in the market, and are often forced to change the product specification at late stages of the product development cycle,” said Eisaku Ohbuchi, director, Core Technology Development, Digital Media Professionals Inc. “By using the Questa register assistant features, we find that our engineers keep up with customers' demand for specification changes in a very flexible manner while maintaining a sharp focus on all the other aspects of verification.”

“The qualification of the Questa functional verification platform for DMP's graphics IP will provide significant value to the many silicon suppliers who are our mutual customers,” said John Lenyo, vice president and general manager, Design Verification Technology (DVT) Division, Mentor Graphics. “Mentor’s functional verification team pioneered much of the work that now defines the UVM, and we continue to invest heavily in tool development and infrastructure to make our users more productive. From advanced debug and visualization of UVM testbenches, to unique stimulus and coverage tools that plug into UVM environments, we are committed to provide our customers with the best platform for functional verification.”

Read more →

Verification Horizons - October 2013 Issue

Volume 9, Issue 3.
Now available, the latest issue of Verification Horizons.

Access the articles below and the complete issue.

Verification Horizons October 2013 articles include:

  • Software-Driven Testing of AXI Bus in a Dual Core ARM System
  • Caching in on Analysis
  • DDR SDRAM Bus Monitoring using Mentor Verification IP
  • Simulation + Emulation = Verification Success
  • Life Isn't Fair, So Use Formal
  • AMS Verification for High Reliability and Safety Critical Applications
  • Assertions Instead of FSMs/logic for Scoreboarding and Verification

Read more →

Pages