Academy News | Verification Academy

Mentor Graphics Veloce Emulation Platform Used by Starblaze for Verification of SSD Enterprise Storage Design

WILSONVILLE, Ore., September 20, 2016 – Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Veloce® emulation platform was successfully used by Starblaze Technology for a specialized high-speed, enterprise-based Solid State Drive (SSD) storage design.

Starblaze performed a detailed and lengthy analysis of the available solutions in the emulation market. The Veloce emulation platform was selected and deployed because of its superior virtualization technology and memory protocol support, rich software debug capabilities and proven track record delivering innovative emulation technology.

“The enterprise SSD market is evolving rapidly, so the SoC (System on a Chip) verification technology we use has to be perfectly aligned with our needs, especially in terms of flexibility and high-performance protocol support,” said Sky Shen, CEO of Starblaze Technology. “After using the Veloce emulation platform on our latest high-performance, enterprise SSD controller project, we are convinced that a virtual solution with extensive software debug capability is the trend for the future of emulation technology.”

In the SSD storage space, it is extremely important for design teams to study the architecture and tune the performance while finding deep hardware bugs in the pre-silicon stage. Starblaze used VirtuaLAB PCIe to provide the host connection to their design on the Veloce emulation platform. The VirtuaLAB PCIe delivers very high debug productivity, and Starblaze was able to use its Software Design Kit “as is” without any modification or adaption. In addition to using Veloce VirtuaLAB, Starblaze used Mentor’s Codelink® software debug capability to support the requirements of their embedded core software debug. In the flash interface side, the Veloce platform provides both HW and SW sparse memory solutions, which permits the necessary tradeoffs in the storage application.

ICE and Virtual: Complementary Technologies

With the Veloce Emulation platform, verification teams have access to the best of both worlds, whether using an ICE-based or virtual emulation environment. In-circuit emulation (ICE), a foundational emulation use model, remains a ‘must have’ for SoC designs that need to connect to real devices or custom hosts where physical hardware is required. The Veloce iSolve™ library offers a full complement of hardware components to build a robust ICE-based flow.

As more verification teams move from an ICE-based flow to a virtual flow, the Veloce emulation platform provides a smooth transition. The Veloce Deterministic ICE App complements ICE by eliminating the non-deterministic nature of ICE and enabling advanced verification techniques: debug, power analysis, coverage closure, and software debug.

Full virtualization is achieved with the Veloce VirtuaLAB environment, which delivers virtual ICE-equivalent, high-speed host protocols and memory devices, allowing for greater flexibility for hardware/software system-level debug, power analysis, and system performance analysis.

“The Veloce emulation platform continues to deliver a comprehensive and robust emulation platform to a broad set of markets that all have unique challenges,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “With Starblaze’s expertise in Flash Controller and SoC design, they quickly recognized the benefits of our VirtuaLAB solution. Our success in working with them is attributed to our in-depth knowledge of the power of a virtual solution, and our timely support in deploying the Veloce emulation platform to meet their specific needs.”

About the Veloce Emulation platform

The Veloce emulation platform uses innovative software, running on powerful, qualified hardware and an extensible operating system, to target design risks faster than hardware-centric strategies. Now considered among the most versatile and powerful of verification tools, emulation greatly expands the ability of project teams to do hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation and performance characterization.

Verification Horizons Blog

Verification Knowledge Exchange.
In this BLOG you will find posts from the Verification Academy's Harry Foster, Verification Horizon's Tom Fitzpatrick and Standard's Advocate Dennis Brophy and a host of other Verification Horizon Contributors.

The Verification Horizons Blog will provide an online forum for updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Latest blog post: >Part 7: ASIC/IC Design Trends - The 2016 Wilson Research Group Functional Verification Study - Harry Foster

Additional blog posts include:

Taming the Verification Debug Monster - Dennis Brophy
Part 6: FPGA Language and Library Trends - The 2016 Wilson Research Group Functional Verification Study - Harry Foster
Part 5: FPGA Verification Technology Adoption Trends - The 2016 Wilson Research Group Functional Verification Study - Harry Foster
Part 4: FPGA Verification Effectiveness Trends - The 2016 Wilson Research Group Functional Verification Study - Harry Foster
3 Things About UPF 3.0 You Need to Know Now - Joe Hupcey III
Part 3: FPGA Verification Effort Trends Continued - The 2016 Wilson Research Group Functional Verification Study - Harry Foster
Part 2: FPGA Verification Effort Trends - The 2016 Wilson Research Group Functional Verification Study - Harry Foster
Part 1: FPGA Design Trends - The 2016 Wilson Research Group Functional Verification Study - Harry Foster
Portable Stimulus Takes an Important Step Forward - Tom Fitzpatrick
Understanding and Minimizing Study Bias (2016 Study) - Harry Foster
Prologue: The 2016 Wilson Research Group Functional Verification Study - Harry Foster
UVM: The Factory Powers Reuse - Tom Fitzpatrick
How to Avoid Metastability on Reset Signal Networks, a/k/a Reset Check is the New CDC - Joe Hupcey III
The first ISO 26262 certified blog post! - Avidan Efody
Portable Stimulus Taking Center Stage at DAC - Tom Fitzpatrick
Standards, Partners and Industry Collaboration Update - Dennis Brophy
5 Things I Learned at the 2016 SAE World Congress - Joe Hupcey III
2016 Bangalore edition of Mentor’s Forum for Verification is round the corner - Pradeep Salla
UVM: The Value of Flexibility - Tom Fitzpatrick
Still waiting… It’s Friday afternoon, and I don’t have my RTL - Rich Edelman
FPGA Prototyping is coming home - Doug Amos
No to Know VIP – Validated! - Pradeep Salla
DVCon USA 2016: Heralding Formal’s New Wave - Joe Hupcey III
DVCon US: UVM Is BIG - Tom Fitzpatrick
Introducing the Verification Academy Patterns Library! - Harry Foster

Mentor Graphics Verification Academy Adds SystemVerilog Course and Patterns Library to Expand Engineers’ Expertise and Resources

WILSONVILLE, Ore., August 9, 2016 – Mentor Graphics Corp. (NASDAQ: MENT) has added to its Verification Academy a new SystemVerilog course and Patterns Library that together help verification engineers increase their expertise, productivity, and design quality. Developed by one of the leading SystemVerilog experts in the industry, SystemVerilog Object-Oriented Programming (OOP) for UVM Verification enables engineers to extend their SystemVerilog skills and keep up to date on the latest concepts, techniques, and methodologies. The searchable and versatile Patterns Library captures solutions for commonly encountered recurring problems, allowing organizations to document and share best practices to improve verification productivity and final design quality.

“The Verification Academy is a comprehensive, straightforward, and accessible resource for UVM-based verification. With the addition of the new Patterns Library, the Academy now provides an example-based, searchable library for verification design patterns,” said Brian Mathewson, lead ASIC verification engineer at SEAKR Engineering. “Supported by Mentor Graphics best-in-industry application engineers, the Verification Academy provides the resources needed to advance verification skills to speed up the design and verification cycle.”

Design and verification patterns provide an optimized, reusable solution to many modern engineering problems. In verification, they are a proven, effective tool for sharing best practices and building skills within a project team. Mentor is broadening adoption of patterns by creating an easily searchable, readily available, and referenceable library that expands the application of patterns for verification. The new Patterns Library extends beyond the coding aspect of simulation testbenches into more general verification concerns, such as specifying assertions, defining input stimulus, and analysis. It reaches across the entire domain of verification—from specification to methodology to implementation. It introduces a systematic set of steps for organizing and documenting patterns in a manner that is applicable across all verification engines, including simulation and emulation.

SystemVerilog skills are in high demand. This new course is presented by recognized SystemVerilog expert Dave Rich, who was involved in the initial development of SystemVerilog and its standardization and continues to be a leading contributor to its expanding capabilities and value. The SystemVerilog OOP for UVM Verification course helps engineers grow their SystemVerilog skills so they can take advantage of the advanced verification tools and technologies demanded by the needs of the industry.

“With over 75% industry-wide adoption, SystemVerilog is now the predominant language used for verification today. Our new Verification Academy SystemVerilog course, along with our other popular UVM courses, provides an excellent educational resource for advancing verification skills,” said Harry Foster, chief scientist, Design Verification Technology Division at Mentor. “The new Verification Academy Patterns library provides provable solutions to many challenging assertion specification and UVM testbench problems—in an easily discoverable, referenceable, and relatable format.”

Seminar: Functional Verification Tech Day 2016 - September 27th | Herzliya, Israel

Overview

At this event you will learn about the solutions provided by Mentor Graphics that answer questions raised by the trends in the industry that are pushing the need for advanced verification, understand how to adapt to this and see how taking a new look at your verification methodologies and tools can help you build higher quality, on-time products enabling you to be more competitive in today's evolving market.

Increase in complexity creates a widening gap between design abstraction and verification when traditional verification approaches come up short. As a result, the balance is shifting as more users want and need to adopt modern verification practices in order to be competitive.

Delegates will be exposed to features, utilities and working methods that simplify the work required to reach final result. The presentation lectures will be complemented with practical demonstrations.

View conference agenda.

Learn more and register.

Seminar: Enterprise Debug & Analysis - October 6th | Santa Clara, CA

Overview

Design verification methodologies are in an endless race to catch up with exploding verification needs. As soon as the verification industry standardizes on a methodology, a new set of requirements emerges. While methodologies like coverage-driven test ranking and sophisticated checkers can help focus the verification results on the most high-value data points, a real live person must still sift through all of the output and navigate the failure analysis–bug identification–fix–validate cycle. The debug challenge is big and is only growing.

Indeed, based on semi-annual customer surveys debug is now exceeding 39% of an engineer's time, which is more than any other single verification task. Clearly, improving debug productivity for an enterprise flow from block to system pre-silicon verification, virtual prototyping, emulation, as well as post-silicon validation is critical to stay on schedule and simultaneously meet quality goals. Join us for this comprehensive seminar to learn the very latest verification techniques.

Learn more and register.

Seminar: FPGA Network – Design Tools & Methodologies - October 11th | Swindon, United Kingdom

Overview

The October meet up of the NMI FPGA Network will share experiences of how design tools and methodologies impact the schedule, solve difficult problems, affect quality, optimize architecture, bridge hardware and software communities. It will provide a stage for end users (the good workmen) and solutions and service providers (also good workmen) to praise what works well so all can benefit from the knowledge.

Featured Session:

Staying Competitive by Evolving Your FPGA Verification Methodologies

FPGA vendors continue to create new ways for FPGA users to efficiently design into complex FPGAs. This has created a widening gap between design abstraction and verification on which traditional verification approaches come up short. As a result, more FPGA users want and need to adopt modern verification practices to be competitive. Unfortunately, they don't always know where to start or find the cost/risk too great. In this session you will learn about themes in the industry that are pushing the need for advanced verification, understand how FPGA users are adapting and see how a new look at verification methodologies helps build higher quality, on-time products.

Learn more and register.

Seminar: Verification Academy Live: Clock Domain Crossing (CDC) Tips for Success - November 1st | Austin, TX

Overview

Metastability from the intermixing of multiple clock signals is not modeled by simulation. Unless you leverage exhaustive, automated Clock Domain Crossing (CDC) analyses to identify and correct problem areas, you will inevitably suffer unpredictable behavior when the chip samples come back from the fab. These problems are only compounded when your reset signaling network gets caught up in the mix as well. Hence, the focus of this free, half-day Verification Academy seminar is on how you can get the most out of automated, formal-based CDC analysis – including the latest techniques and real-world customer case studies. Register today!

View the seminar agenda and register.

Mentor Graphics Veloce Emulation Platform Helps Barefoot Networks Verify the World’s First Fully Programmable Switch

WILSONVILLE, Ore., July 19, 2016 – Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Veloce® emulation platform was successfully used by Barefoot Networks, a pioneer in building user-programmable and high-performance network switches, to verify its 6.5Tbps TofinoTM switch. Barefoot chose the Veloce emulation platform for its high capacity, superior virtualization technology, remote access option and proven track record in networking design verification.

Barefoot Networks benchmarked the different emulators available, and after a careful and lengthy evaluation, decided the Veloce platform was the only emulator able to handle the large and complex Barefoot Networks design.

“The Veloce emulation platform gave us the capacity we needed to verify our programmable, networking-specific and interconnect-dominated design,” said Dan Lenoski, VP of Engineering, Barefoot Networks. “Beyond the fundamental strengths of the Veloce emulation platform, we were also able to take advantage of their proven hardware+software co-emulation, which is critical for verifying a programmable networking device.”

Verification Horizons - June 2016 Issue

Verification Horizons Complete Issue:

Download - 16.7 MB
Web Browser - 3.7 MB

Access the articles below and the complete issue.

Verification Horizons June 2016 articles include:

Join SystemVerilog Expert Dave Rich for the latest course addition to the Verification Academy video library:

The SystemVerilog OOP for UVM Verification course is aimed at introducing the OOP features in SystemVerilog most commonly used by the UVM in the simplest form. No UVM is presented in this course, but the examples shown are directly applicable to the underlying principles that make the UVM work.

SystemVerilog OOP for UVM Verification

Sessions include:

Classes
Inheritance and Polymorphism
OOP Design Pattern Examples

View the new SystemVerilog course.

Mentor Graphics Emulation Services Accelerates Verification with the Veloce Emulation Platform

Continental achieves first-pass success using Mentor Emulation Services

WILSONVILLE, Ore., April 14, 2016 - Mentor Graphics Corporation (NASDAQ: MENT) today announced that Mentor® Emulation Services, which combines the Veloce® emulation platform with expert services and IP, accelerates verification and reduces the risks associated with system-on-chip (SoC) design. Mentor Emulation Services brings the Veloce emulation platform to companies with an immediate need who choose to purchase at a later time, or who own the Veloce platform and need additional short-term capacity.

International automotive supplier Continental used Mentor Emulation Services for the verification of a complex SoC that achieved first-pass success, on schedule.

“Getting first-pass success was an extraordinary achievement for a design of the size and complexity we were verifying,” said Theodor Maier, director of microelectronic integration, Corporate Systems & Technology at Continental. “In our case, the decision to forego FPGA prototyping came very late in the project phase when we only had three to five months before tapeout. Mentor Emulation Services helped us to reduce the risk in this very big challenge, giving us the confidence to go to tapeout on schedule.”

Mentor Graphics and Ixia Collaborate to Accelerate Verification of Networking Chips

WILSONVILLE, Ore., April 12, 2016 – Mentor Graphics Corp. (Nasdaq: MENT), today announced a collaboration with Ixia, a leading provider of network testing, visibility, and security solutions. As a result, Mentor is integrating Ixia’s virtual edition test product family – IxNetwork® Virtual Edition (VE) – with the Mentor® Veloce® emulation platform to accelerate the verification of complex networking chips. As part of this collaboration, Ixia joined the Mentor OpenDoor® program.

As a result, networking customers have the ability to seamlessly integrate an Ixia virtual environment into an emulation-based verification flow, bringing the powerful advantages of emulation to the lab environment. This allows the reuse of traffic flow generation scripts for greater efficiency and improved debug, and gives customers the ability to de-risk the challenges of complex chip designs.

The resulting new Mentor product, the Veloce Virtual Network (VN) App, was driven by the Veloce team based on the requests and support of mutual customers. The development work needed to complete the Veloce VN App was accomplished through the cooperation of the R&D organizations at both Mentor and Ixia.

“Emulation provides a huge performance advantage for full-chip verification,” said, Scott Westlake, Vice President Business Development, Ixia. “It is natural for Mentor and Ixia to collaborate and drive a ‘shift left’ that expands the use of virtualized testing to accelerate the delivery of networking chips to market.”

Mentor Graphics Announces Qualification of Hewlett Packard Enterprise Hardware: Cuts Compile Time for Veloce Emulation Platform by up to 50 Percent

WILSONVILLE, Ore., March 22, 2016 - Mentor Graphics Corp. (NASDAQ: MENT), today announced that the HPE ProLiant DL380 Gen9 and HPE ProLiant DL580 Gen9 servers from Hewlett Packard Enterprise (HPE) have been qualified for use with the Veloce® emulation platform. Use of these servers, combined with recent updates to the Veloce OS3 operating system, has reduced the compile time for the Veloce platform by up to 50 percent.

The rigorous qualification process defined by Mentor confirms the low-latency, high-bandwidth communication between the HPE ProLiant DL380 Gen9 and the Veloce emulator, where the HPE ProLiant DL380 Gen9 servers function as the co-model and run-time hosts in a Veloce configuration. The HPE ProLiant DL580 Gen9 server functions as the compile server and is qualified and tuned to significantly reduce end-to-end Veloce compile time.

“The hardware qualification process is part of our commitment to customers to make the installation and use of the Veloce platform as rapid and issue-free as possible,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division.

The HPE ProLiant Gen9 rack server portfolio offers flexibility and enhanced system performance to run compute intensive workloads in any environment. Built for general purpose compute, the HPE ProLiant DL380 Gen9 Server delivers exceptional performance and expandability in the HPE 2P rack portfolio to provide customers with sustained reliability, serviceability and availability. The four-socket HPE ProLiant DL580 Gen9 server, designed for data intensive workloads, offers dependable performance for mission-critical enterprises, business intelligence and database applications.

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