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Verification Horizons Blog

Verification Knowledge Exchange.
In this BLOG you will find posts from the Verification Academy's Harry Foster, Verification Horizon's Tom Fitzpatrick and Standard's Advocate Dennis Brophy and a host of other Verification Horizon Contributors.

The Verification Horizons Blog will provide an online forum for updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Latest blog post: DAC 2022: The Digital Twin Reimagined – One Model To Rule Them All? - Joe Hupcey III

Additional blog posts include:

DAC 2022: Siemens EDA Experts Share Practical Cloud Solutions - Joe Hupcey III
Learn How to Verify PCIe Integrity and Data Encryption (IDE) Security Logic at the 2022 PCI SIG Developer Conference - Joe Hupcey III
Siemens EDA at Verification Futures 2022 - Harry Foster
Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking - Joe Hupcey III
Verilog & VHDL Debug & Weeding - Rich Edelman
Siemens EDA at the 59th Design Automation Conference - Harry Foster
Clearing the Fog of ISO 26262 Tool Qualification - Joseph Dailey and Jake Wiltgen
Do You Know for Sure Your RISC-V RTL Doesn’t Contain Any Surprises? - Joe Hupcey III
Key findings of a crucial safety lifecycle evaluation - Trey Reeser
Navigating the Intersection of Safety and Security - Jake Wiltgen
Growing Complexity of Automotive ASICs - Harry Foster
See you at GOMACTech - Ray Salemi
Verification Horizons DVConUS 2022 Issue is Out! - Tom Fitzpatrick
Preview of DVCon 2022 — How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage - Joe Hupcey III
FPGA Retargeting - Ray Salemi
Siemens EDA @DVConUS 2022 - Tom Fitzpatrick
Guidelines to a successful ISO 26262 Lifecycle - Jake Wiltgen
Getting your Safety Architecture just right - Chuck Battikha
The configurability dilemma creating safe ICs - Jake Wiltgen & Chuck Battikha
The importance of effective Safety Analysis - Jake Wiltgen
The Many Flavors of Equivalence Checking: Part 6, FPGA-focused Equivalency Checking Flows - Joe Hupcey III
Odds and Ends - Ray Salemi
Logging in pyuvm - Ray Salemi
Build Your Career by Attending the Static & Formal Verification University at DAC 2021 - Joe Hupcey III
The UVM Factory - Ray Salemi
A UVM Scoreboard: Does it really have to be that hard? - Rich Edelman
Non-stick surfaces and RTL design - Chris Giles
Webinar Preview: Practical Flows for Continuous Integration - Neil Johnson
HDL Coding Standards for DO-254 - Jake Wiltgen
The configuration database in pyuvm - Ray Salemi
Debugging SoCs Can Be Complicated - Andrew Meier and Tomasz Piekarz
Siemens EDA at the 58th Design Automation Conference - Harry Foster
TLM 1.0 in pyuvm - Ray Salemi
Design Linting for ISO 26262 - Jake Wiltgen
How Can You Say That Formal Verification Is Exhaustive? - Joe Hupcey III
Leave the House With a Clean Design - Chris Giles
Python and the UVM - Ray Salemi
Learn Formal the Easy Way - Joe Hupcey III
Class Variables and $cast - Chris Spear
SPICE Turns 50! - Dennis Brophy
Deploying Formal in a DO-254 Program - Jacob Wiltgen
Class Variables and Assignments in SystemVerilog - Chris Spear
Qrun-ing Optimized Build Flows in Questasim - Neil Johnson
Runtime checks with the $cast() method - Chris Spear
Verification Class Categories - Chris Spear
SystemVerilog Class Variables and Objects - Chris Spear
Verification Academy UVM Video Courses Updated! - Tom Fitzpatrick
Accellera FuSa WG: White paper released! - Jacob Wiltgen
Explanation of “Verification” in a DO-254 program - Jacob Wiltgen
PCIe Gen6 verification – the PCI Express generation comes of age - Gordon Allan
Expediting Simulation Turn-around Time with Incremental Build Flows - Neil Johnson
GSA Leadership Summit: New Paradigms – New Opportunities - Dennis Brophy
Orchestrating an ISO 26262 Fault Campaign - Jake Wiltgen
DVCon USA 2021 Best Paper Report – Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt - Joe Hupcey III

On-Demand Recordings:

Sessions from DVCon US illustrated how design and verification teams can improve design quality to reduce ASIC and FPGA bugs before the integration phase.

Verification Horizons - March 2022 Issue

Verification Horizons Articles:

The Many Flavors of Equivalence Checking – A Blog Series

In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation, analog simulation, RF simulation, and even simulators for the flow of materials across a factory floor. One term, accurately describing very different tools that are optimized for a plethora specific jobs. Similarly, “logic equivalence checking” (LEC) also applies to a number of tools that cover a wide variety of high-value verification tasks. Even experienced engineers can get tripped up in mapping equivalency checking requirements to the corresponding tool and work flow, hence this series of posts to enumerate what is out there.

Verification Horizons:

How to Reduce the Complexity of Formal Analysis – A Blog Series

When using formal property checking, users often encounter “inconclusive” results; which means that the combined complexity of the design, assertions, and assumptions is beyond the capacity of the tool to compute in one run. In this series of posts we will show how to address this by evaluating the relevant active logic, locating the assumptions and design elements that could cause an inconclusive result, and how to estimate the complexity of the assertions themselves. Then we will discuss methods for reducing the complexity of each of these elements so the analysis will yield a solution.

Verification Horizons:

Guidelines to a successful ISO 26262 Lifecycle – A Blog Series

This series will provide safety managers, project leads, and practitioners a list of challenges that exist in various points in the ISO 26262 Safety lifecycle where considerable thought should be given and a plan formed prior to execution of the task or possibly even the development lifecycle.

Verification Horizons:

Getting your Safety Architecture just right
- Learn the options, tradeoffs, and pitfalls when defining an IP or IC safety architecture
The configurability dilemma creating safe ICs
- Learn how design and safety architecture configurability adds complexity to the delivery of the safety case and work products
The importance of effective Safety Analysis
- Learn how effective early cycle safety analysis anchors a successful safety lifecycle

The Python for Verification Series

This series of blog posts introduction Python as a verification language. cocotb an excellent way for Python to communicate to simulators. And pyuvm as a way to write UVM testbenches on top of cocotb.

Verification Horizons:

Verification Learns a New Language
- Are SystemVerilog or VHDL the only languages for testbench design? What about Python?
Introduction to Coroutines
- Why a Python feature intended for I/O and asynchronous communication is perfect for verification.
Cocotb Bus Functional Models
- How to use cocotb to write bus functional models in Python.
Python and the UVM
- An introduction to pyuvm and how we can use it to write UVM code on top of cocotb.
TLM 1.0 in pyuvm
- We’ll examine pyuvm’s implementation TLM 1.0 using simple producer/consumer examples. First we’ll handle blocking operations.
The configuration database in pyuvm
- Now we turn our attention to some of the UVM’s utilities and how we use them in Python. The first of these is the UVM configuration database.
The UVM Factory
- The pyuvm implements the UVM factory as it is described in the specification, removing elements that complicated the factory because of SystemVerilog typing.
Logging in pyuvm
- This blog post provides a brief overview of logging and compares it to UVM reporting. Then it discusses logging in pyuvm.
Odds and Ends
- This final blog post in the series discusses odds and ends that may have gotten little attention in the blog posts or may not have been invented when the blog post was written.

Resources:

The Verification Horizons example code
- This Git repository contains the working code used as examples in the above blog posts.
Verification Learns a New Language: An IEEE 1800.2 Python Implementation
- This session from DVCon 2021 introduces `pyuvm`, a Python implementation of IEEE Spec 1800.2. It discusses the Python tricks used to implement UVM features such as the factory, FIFOs, and config_db.

Verification Horizons - September 2021 Issue

Verification Horizons Articles:

Verification Horizons - March 2021 Issue

Verification Horizons Complete Issue:

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Verification Horizons Articles:

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