X in uvm_reg transactions

Hi,

I have an issue where teh DUT returns an X for register read but the reg2bus still sees it as a 0.

When I was going over the uvm_reg_bus_op struct the type for data is uvm_reg_data_t which is only 2-state.

Is there a way to override this argument to support 3/4-state? Maybe uvm_reg_data_logic_t?

Please let me know.

Thanks in advance!

Vignesh

In reply to vigneshr:

I don’t see any support to override this struct uvm_reg_bus_op. if this 'hX propogation is illegal then you can set the rw.status enum for invalid case. that’s how you can monitor such operation.

In reply to vigneshr:

Hi,
I have an issue where teh DUT returns an X for register read but the reg2bus still sees it as a 0.
When I was going over the uvm_reg_bus_op struct the type for data is uvm_reg_data_t which is only 2-state.
Is there a way to override this argument to support 3/4-state? Maybe uvm_reg_data_logic_t?
Please let me know.
Thanks in advance!
Vignesh

I believe it is not a good idea to return a ‘x’ when reading a register. ‘x’ means it can be any value ('b0, 'b1, 'bz or something else or any combination of these values.
Physically seen a register should never hold such a value. Your RTL model should take care of this.

Yes, its not a good thing if the RTL returns a X and thats exactly the reason why I want to catch it. This could sometimes happen for RO registers as well.

So my problem is the even the status is UVM_IS_OK which I believe is because the data type is 2 state and I’m not sure how I can check within reg2bus that an X was seen at the interface if the data is gonna be 0 anyway. Any help is appreciated.

In reply to vigneshr:

Unfortunately I do not get your point. If you want to read a X from a register you have to code this in your RTL. What is the synthesis tool doing with an x? It does not know it. I do not believe it has a prctical background what you are requesting.

Back to your original question. In your case I’d try to overwrite the struct uvm_reg_bus_op with an entry uvm_reg_data_logic_t.

In reply to chr_sue:

How do I override a UVM struct? I’m not sure if this ones registered with the factory?

In reply to vigneshr:

I’d make a copy of the base class library implementation, make the modifications with respect to the data type and put this to my register related database (where bus2reg and reg2bus are implemented).

In reply to vigneshr:
Did you find any workaround to resolve the problem.one thing we can do is simply change the data type of uvm_reg_data_t variable from bit to logic in src/reg/uvm_reg_model.svh file.I ran simple test case and I can see X propagation to top level sequence. I’m not sure how much it is correct doing this change in uvm library and other consequences but simply it worked.

I’m guessing this issue might have already addressed in UVM Accellera version.

code change
//typedef bit unsigned [UVM_REG_DATA_WIDTH-1:0] uvm_reg_data_t ; typedef logic unsigned [UVM_REG_DATA_WIDTH-1:0] uvm_reg_data_t ;

Thanks,
Siva Sankar