In reply to vigneshr:
Did you find any workaround to resolve the problem.one thing we can do is simply change the data type of uvm_reg_data_t variable from bit to logic in src/reg/uvm_reg_model.svh file.I ran simple test case and I can see X propagation to top level sequence. I'm not sure how much it is correct doing this change in uvm library and other consequences but simply it worked.
I'm guessing this issue might have already addressed in UVM Accellera version.
//typedef bit unsigned [`UVM_REG_DATA_WIDTH-1:0] uvm_reg_data_t ;
typedef logic unsigned [`UVM_REG_DATA_WIDTH-1:0] uvm_reg_data_t ;