Writing randomized data in a uvm_reg test

UVM
,
1

I declared “rand uvm_reg_data_t data;” in my test class.

And I am doing
foreach(regs[i]) begin
assert(this.randomize());
regs[i].write(status, data);
end

But how do I randomize the filed ‘data’ in the test?

Regards,
Ravi

2

Because of the very short code snipped I cannot say this.randomize is correct. But calling the randomize method on a certain reg is randomizing the data fields. Instead of using the simple read you should call the update method, like this (see a code snippet of an example:

apb_regs.get_registers(data_regs);
data_regs.shuffle();
foreach(data_regs[i]) begin
// Randomize register content and then update
if(!data_regs[i].randomize()) begin
uvm_error(get_type_name(), $sformatf("Randomization error for data_regs[%0d]", i)) end data_regs[i].update(status, .path(UVM_FRONTDOOR), .parent(this)); end data_regs is a queue containing all registers. The shuffle method allows top access the regs in random order. If you want to see you can include after the ranomization an uvm_info, displaying the reg data.

3

Thank you!

4 
 foreach(registers[i]) begin
      if ((uvm_resource_db#(bit)::get_by_name({"REG::",registers[i].get_full_name()},"NO_REG_TESTS", 0) != null) || (uvm_resource_db#(bit)::get_by_name({"REG::",registers[i].get_full_name()},"NO_REG_ACCESS_TEST", 0) != null )) begin
      `uvm_info(get_type_name(), $psprintf("NO_REG_TESTS is defined for this register=%0h so ignore R/WR",registers[i]), UVM_LOW);
      end
      else begin 
      $display("Inside Wie_ral_basic_access_sequence RAL write function");
      `uvm_info("Write function","Inside Wie_ral_basic_access_sequence RAL write function", UVM_LOW);
        wr_data=$random;
        registers[i].write(status, wr_data, .parent(this));
      end
    end

I am trying like this but regiter size is not increasing and not going inside else part so write is not happening.

I am getting like this info/display in log file

regmodel size : 0
UVM_INFO /nfs/iind/disks/ba_WIE_fe_ver_disk01/aavvarux/wie_verif_29AUG/verif/wie_tb/env/sequences/ral_sequences/wie_ral_basic_access_sequence.sv(65) @ 1033000000: reporter@@reg_seq [get_full_name()] RAL registers = '{}

Can anyone help.Thanks in advance…!

5

In reply to Manikanta2595:

I believe you are doing wrong with getting all registers.
You should follow my approach above, using the method get_registers.

6

In reply to chr_sue:

Iam following the same way,as yours.

uvm_status_e status;
uvm_reg registers[$];
reg_model = ral_sys_TOP::type_id::create("reg_model");

`uvm_info("body_ral_seq","Entered to body of wie_ral_basic_access_sequence", UVM_LOW);
reg_model.get_registers(registers, UVM_HIER);
$display("\n regmodel size : %0d",registers.size());
`uvm_info("get_full_name()",$psprintf("RAL registers = %p", registers), UVM_LOW);
foreach(registers[i]) begin
    if ((uvm_resource_db#(bit)::get_by_name({"REG::",registers[i].get_full_name()},"NO_REG_TESTS", 0) != null) || (uvm_resource_db#(bit)::get_by_name({"REG::",registers[i].get_full_name()},"NO_REG_ACCESS_TEST", 0) != null )) begin
             `uvm_info(get_type_name(), $psprintf("NO_REG_TESTS is defined for this register=%0h so ignore R/WR",registers[i]), UVM_LOW);
          end
    else begin
      $display("Inside Wie_ral_basic_access_sequence RAL write function");
      `uvm_info("Write function","Inside Wie_ral_basic_access_sequence RAL write function", UVM_LOW);
      wr_data=$random;
      registers[i].write(status, wr_data, .parent(this));
    end
end
7

In reply to Manikanta2595:

I do not understand what you are doing here:

foreach(registers[i]) begin
if ((uvm_resource_db#(bit)::get_by_name({"REG::",registers[i].get_full_name()},"NO_REG_TESTS", 0) != null) || (uvm_resource_db#(bit)::get_by_name({"REG::",registers[i].get_full_name()},"NO_REG_ACCESS_TEST", 0) != null )) begin
`uvm_info(get_type_name(), $psprintf("NO_REG_TESTS is defined for this register=%0h so ignore R/WR",registers[i]), UVM_LOW);
end
8

In reply to chr_sue:

Hi chr_sue,
I am using the below peice of code , to write in to the registers,But iam facing the fatal error.
code :
reg_model.get_registers(registers, UVM_HIER);
foreach(registers[i]) begin
wr_data=$random;
registers[i].write(status, wr_data, .parent(this));
end

UVM_FATAL @ 1033000000: reporter@@reg_seq [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in reg_seq

My sequence is :
virtual task body();
super.body();
`uvm_info(“body_ral_vr_seq”,“Entered to body of wie_ral_basic_access_vr_sequence”, UVM_LOW);
reg_seq=wie_ral_basic_access_sequence::type_id::create(“reg_seq”);
reg_seq.reg_model= p_sequencer.reg_model;
reg_seq.start(null);
UVM_LOW);
endtask : body

9

In reply to Manikanta2595:

If your sequencer has to generate seq_items you have to specify this sequencer and to start the sequencer on this sequencer.You can only start a virtual sequence without a virtual sequencer.