Why UVM has desired and mirrorred concept in the RAL model

UVM
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Dear All,

I’m just getting started the UVM methodology and come across RAL model.
In especially, there is mirrored and desired concept in RAL model.
But I’m confused that why does UVM use desired and mirrorred concept in RAL model?
Can’t we just directly tests the registers in DUT without desired and mirrorred?

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In reply to UVM_LOVE:

One of the key things is to hold the registers in the DUT and in the shadow synchronous.
With set or randomize from a sequence the content of the shadow changes, but the DUT have then other content. The shadow content will be considered as the desired values. mirror reads the content from RTL registers. This is now the mirrored value. Now we have to make sure both values are the same. To synchronize the register content you have to call update.

3

In reply to chr_sue:

In reply to UVM_LOVE:
One of the key things is to hold the registers in the DUT and in the shadow synchronous.
With set or randomize from a sequence the content of the shadow changes, but the DUT have then other content. The shadow content will be considered as the desired values. mirror reads the content from RTL registers. This is now the mirrored value. Now we have to make sure both values are the same. To synchronize the register content you have to call update.

I know how they work, But I can’t understand why do they need for register test.
We can just register test in DUT without RAL model by putting the randomized value or intention value.

4

In reply to UVM_LOVE:

The RAL approach is not only for the test of registers. It can be also used in a scoreboard to make decisions depending on register content. In this case you can simply make a get on the corresponding register without doing a complete bus cycle.

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In reply to chr_sue:

In reply to UVM_LOVE:
The RAL approach is not only for the test of registers. It can be also used in a scoreboard to make decisions depending on register content. In this case you can simply make a get on the corresponding register without doing a complete bus cycle.

Hi chr_sue & UVM_LOVE
Im working on RAL. Im not able to figure how to get the desired value and mirrored value for comparision and had some other confusions.
So if you can help me by giving some reference to RAL it will be helpful to me
Thank You