Why UVM allows connecting multiple exports/imps to a single put port

UVM
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1

Why UVM would allow connecting multiple exports/imps(uvm_blocking_put_imp) to a single put port(uvm_blocking_put_port) (because it only writes to a single put implementation)?

function new (string name,
uvm_component parent,
int min_size=2,
int max_size=2)

Because UVM allows setting min_size to 2, Expectation was it will write to both the put implementations(if two are connected). But it’s not happening.

I understand analysis port should be used for such scenarios but in that case the new method should have been restricted for the same.

Thanks,
Prasad