Since the UVM is written in SystemVerilog, it is by nature procedural. There is a built-in scheduler that executes the various phases (build, connect, run, etc) automatically. It is up to you to write the code for each required phase in any component that you create, particularly agents, drivers and monitors, as well as in the uvm_test and uvm_env. For stimulus, that will be defined in the body task. Please see the UVM Cookbook and/or the UVM Basics and Advanced UVM video courses for more details.