Why module is static and class is dynamic?

As of i know memory for module is created at compilation time and we cannot modify it and for class also memory is created at compilation time and during simulation we can modify the size.

Is it correct?

In reply to ranju.ranjitha555@gmail.com:

Modules and classes are both containers for declarations.

Modules instances get created at compile/elaboration. The declarations in a module have static lifetimes, meaning they exist from before time 0 until the simulation ends. They cannot be created or destroyed during simulation.

Class instances only get created during simulation. The declarations inside a class have dynamic lifetimes, meaning they get created or destroyed by executing procedural code.

Please see
https://verificationacademy.com/forums/systemverilog/when-should-be-program-block-dynamic-or-static-members-static-program-block-members-automatic-program-blocks#reply-38825
https://verificationacademy.com/forums/systemverilog/what-exact-difference-between-static-tasks/functions-and-automatic-tasks/functions-please-explain-clear-example#reply-44935

In reply to ranju.ranjitha555@gmail.com:

modules are used to describe a hardware, so hardware is static~
classes are used to describe a testbench and as testbench can be changed, hence they are dynamic.

Agree, not 100% true, but…