Why the FATAL error

Hi all, I am a beginner in UVM and trying a simple code to randomize two variable but getting some unwanted errors.Any suggesting will be appreciated.

edaLink


//=========== code starts here ============//

`include "uvm_macros.svh"
package my_pkg;
import uvm_pkg::*;
//sequence_item class
class my_transaction extends uvm_sequence_item;
  `uvm_object_utils(my_transaction)
  rand logic [3:0] a;
  rand byte b;
  constraint c_a {a>5;a<15;}
  constraint c_b {b>0;b<10;}
  function new(string name = "");
    super.new(name);
  endfunction
endclass
//sequence class
class my_sequence extends uvm_sequence #(my_transaction);
  `uvm_object_utils(my_sequence)
  my_transaction req;
  function new(string name = "");
    super.new(name);
  endfunction
  task body();
    repeat(10) begin 
      req=my_transaction::type_id::create("req");
      start_item(req);
      if (!req.randomize()) begin
        `uvm_fatal("MY_SEQUENCE", "Randomize failed.");
      end
      $display("a=%0d b=%0d",req.a,req.b);
      finish_item(req);
    end 
  endtask
endclass
class sequencer extends uvm_sequencer #(my_transaction);
  `uvm_component_utils(sequencer)
  function new(string name,uvm_component parent=null);
    super.new(name,parent);
  endfunction  
endclass  
class driver extends uvm_driver #(my_transaction);
  `uvm_component_utils(driver)
  function new(string name,uvm_component parent=null);
    super.new(name,parent);
  endfunction 
endclass
//test class
class my_test extends uvm_test;
  `uvm_component_utils(my_test)
  function new(string name,uvm_component parent=null);
    super.new(name,parent);
  endfunction 
  my_sequence seq;
  sequencer ss;
  driver div;
  function void build_phase(uvm_phase phase);
    seq=my_sequence::type_id::create("seq");
    ss=sequencer::type_id::create("ss",this);
    div=driver::type_id::create("div",this);
  endfunction 
  function void connect_phase(uvm_phase phase);
    div.seq_item_port.connect(ss.seq_item_export);
  endfunction
  
  task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    begin 
    seq.start(ss);
    end
    phase.drop_objection(this);
  endtask
endclass
endpackage : my_pkg

module tb();
  import my_pkg::*;
  import uvm_pkg::*;
  initial begin 
    run_test("my_test");
  end 
endmodule 

//================== END ==================//

In reply to designMaster:

Please use the SV code tags to make your code more readble.
In your code you do not define the type sequencer, i.e. there is no class defined like this

class sequencer extends uvm_sequencer #(my_transaction);

In reply to chr_sue:

Actually I don’t need any manual sequencer that’s why have directly instantiated the sequencer by

uvm_sequencer #(my_transaction) sequencer;

In reply to designMaster:

You have a reference like this in your code:
sequencer ss;

If you want to use the type_idd create method you have to define a seperate class for your sequencer and to register this with the factory.

And you have some additional weaknesses in your code. See the corrected code here:

The main point is now you are missing a driver. You are creating currently 1 seq_item. Then your tesbench is stucking and stopping by a timeout.

In reply to chr_sue:

Thanks for the correction you made.But I am getting fatal error while running the code.

In reply to designMaster:

The fatal is caused by a timeout:
UVM_FATAL /playground_lib/uvm-1.2/src/base/uvm_phase.svh(1491) @ 9200000000000: reporter [PH_TIMEOUT] Default timeout of 9200000000000 hit, indicating a probable testbench issue

As I said this timeout appears because of the missing driver. Your sequencer generates 1 transaction. But this transaction is not processed by the driver. The sequencer is waiting. The timeout stops the simulation.

In reply to chr_sue:

Its not being cleaned even I added the driver.

In reply to designMaster:

In your driver you do not process the transaction. The run_phase is missing.
See a solution here:

In reply to chr_sue:

I am really really helped by the solution you provide.Thank you very much.