Why don't driver wait clock when driving empty sequences?

UVM
1

In my sequence


class wait_1_clock_c extends uvm_sequence;

  `uvm_object ...
  function new ...

  task body();
    `uvm_info(get_full_name(), "wait 1 clock ... ", UVM_LOW)
  endtask

endclass
//------------------------------------------------
class my_seq extends uvm_sequence#(my_item_c);

  my_item_c      my_item;
  wait_1_clock_c wait_1;

  `uvm_ojbect ...
  function ...

  task body();
    repeat(5) `uvm_do(my_item)
    repeat(3) `uvm_do(wait_1)
    repeat(5) `uvm_do(my_item)
  endtask

endclass

I think ‘my_item’ is randomized & driven in first 5 clocks and waits 3 clocks and is randomized & driven after 5 clocks.

But, In dump & log, ‘my_item’ is randomized & driven in 10 clocks without waiting
( ‘wait_1’ was sent 3 times in the same time )

Why did this situation happen?

2

In reply to HanP:

Your sequence does not know anything about clock cycles. This timing has to be implemented in your driver where the pinlevel signals are available.

3

In reply to chr_sue:

My driver is here


class my_driver_c extends uvm_driver#(my_item_c);

  ...

  virtual task run_phase(uvm_phase phase);
    @(posedge my_if.nReset);
    
    forever begin
      seq_item_port.get_next_item(req);
      my_if.a = req.a;
      ...
      my_analysis_port.write(req);
      @(posedge my_if.clk);
      seq_item_port.item_done;
    end
  endtask
endclass

I think ‘uvm_send’ is as follows


start_item(req);
...
finish_item(req);

So, if a sequence doesn’t have any code in its body,
then i think UVM will work like [start_item(seqeunce) → waiting risign edge of clock(driver) → get_next_item(driver) → item_done(driver) → finish_item(sequence)].

Ultimately, I want to make the 1 clock delay sequence doesn’t do anything with no p_sequencer.
It’s impossible?

4

In reply to HanP:

What is wait_1? You could provide with the seq_item a value for doing nothing, exec cuting in the driver only a well-defined number of clock cycles.

5

In reply to chr_sue:

Thank you chr_sue.
So, If i want to send the seq_item with randomizing for 3-clock-cycle and delay for 2-clock and send the seq_item with randomizing for 3-clock-cycle in my sequence, then is this the right code?


class my_seq extends uvm_sequence#(my_seq_item);

  ...

  task body();
     repeat(3) `uvm_do(req)
     repeat(2) `uvm_send(req)
     repeat(3) `uvm_do(req)
  endtask

  ...

endclass
6

In reply to HanP:

I’d add a data member called no_idles to the seq_item like this:

class my_item_c extends uvm_sequence_item;
 ...
 rand int no_idles;
...
endclass

The body task of the sequence looks like this:

  task body();
     repeat(3) `uvm_do_with(req, {no_idles == 0;})
     repeat(2) `uvm_do_with(req, {no_idles == 3;})
     repeat(3) `uvm_do_with(req, {no_idles == 0;})
  endtask

And the run_phase of the driver looks like this:

task run_phase (uvm_phase phase);
  ...
    forever begin
      seq_item_port.get_next_item(req);
      if (req.no_idles > 0)
        repeat(rq.no_idles)
          @(posedge my_if.clk);
      else
        // assign the item values to the virtual interface
     .....
endtask
7

In reply to chr_sue:

I understand your answer. Thank you chr_sue