In reply to chr_sue:
My driver is here
class my_driver_c extends uvm_driver#(my_item_c);
...
virtual task run_phase(uvm_phase phase);
@(posedge my_if.nReset);
forever begin
seq_item_port.get_next_item(req);
my_if.a = req.a;
...
my_analysis_port.write(req);
@(posedge my_if.clk);
seq_item_port.item_done;
end
endtask
endclassI think 'uvm_send' is as follows
start_item(req);
...
finish_item(req);
So, if a sequence doesn't have any code in its body,
then i think UVM will work like [start_item(seqeunce) -> waiting risign edge of clock(driver) -> get_next_item(driver) -> item_done(driver) -> finish_item(sequence)].
Ultimately, I want to make the 1 clock delay sequence doesn't do anything with no p_sequencer.
It's impossible?
