Suppose, I have a clocking block in the interface(let’s say vif) that I am using to connect the testbench to the DUT.
I am using the clocking block to drive(vif.cb.var <= XX) and sample the DUT interface.
- In a typical SV-UVM testbench, which clocking region will be used to drive the signals to DUT? Is it prepone, but I read this is used to sample the signals from DUT?
- When does the execution of the region start for a clock? Is it with the posedge clk or it doesn’t depend on the clock rather all the event regions go in a cyclic fashion?
- Does setting skew for input and output in the clocking block has any effect on the timing regions?
Thanks for your response in advance!