Which is the best way to implement Interrupt monitor and trigger ISR in UVM testbench

UVM
1

Hi
I wanted to implement below

  • Monitor interrupt event based on some address range ( from AXI monitor)
  • Generate some events and this events will be observed in test/virtual sequence to trigger ISR.

I used below approach.
1.Used axi vip monitor callbacks to sample write/read address phase transaction.
2.send this to subscriber which decodes and generates events ( stores in even_pool)
3. wait for event in virtual sequence and trigger ISR.

Can some one suggest is this approach is fine or suggest is any best approach.
Thanks

2

In reply to Vijay56:

Look to the Verification Academy interrupt examples here:
https://verificationacademy.com/cookbook/code-examples