In the following program coding line,
class updn_seq_item extends uvm_sequence_item;
this line means uvm_sequence_item is a base class and updn_seq_item is a sub class derived from base class. Now, my doubt is-where does this parent/base class come from? I have not seen it being declared anywhere else in the program. What is its orgin?
SystemVerilog supports some concepts of Object-Oriented Programming (OOP) in its specification of class types. Probably best to study some fundamental OOP concepts and principles so that you would have a clearer understanding of why UVM the class library, implemented in SystemVerilog the language, is the way it is.