When creating UVM testbench from the scratch, is there any suggestions?

UVM
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I have two-year experience in IC Verification, but I just wrote testcases in my first job, because the project I took over already had testbench, I was assigned to write testcases so I am totally puzzled when I need to create a testbench for a totally new project in my current company, could you recommend some books about testpoint and testplan writing before writing my testbench? what should i do and what suggestion when participating in a totally new project?

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In reply to Marina.Miao:

You could try the UVM cookbook UVM | Verification Academy

It is quite comprehensive.

HTH,

-R

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In reply to Marina.Miao:

I have two-year experience in IC Verification, but I just wrote testcases in my first job, because the project I took over already had testbench, I was assigned to write testcases so I am totally puzzled when I need to create a testbench for a totally new project in my current company, could you recommend some books about testpoint and testplan writing before writing my testbench? what should i do and what suggestion when participating in a totally new project?

You are asking 2 questions. My answers are here:
(1) For creating a testbench use a UVM Framework Generator. A helpful generator (free of charge) can be found here: https://www.doulos.com/knowhow/sysverilog/uvm/
(2) For testplans there existing different approaches. I’m using an Excel-Sheet. You can download an example as pdf from here: Dr. Christoph Suehnel - Verification Planning & Management