What's the difference between an export and imp?

UVM
1

Most of my implementations have been a port connected to an imp like a connection between a driver and sequencer.
I’m confused with “export”. So what’s the difference between an export and imp.
TIA.

2

You should check out How TLM Works | Advanced UVM | UVM/OVM Verification Methodology | Verification Academy

Basically, both exports and imps provide the implementations of whatever methods your TLM port requires. The difference is an export is an indirect connection to an implementation. It it normally used when when there is component hierarchy involved. A port of a scoreboard may connect to an export of an agent. However, you do not need to know of the agent is the actual imp of the TLM method, or if it is just exporting an imp from a lower level component.

3

In reply to dave_59:

Thanks dave_59. Excellent explanation.
I wandered through verificationacademy and stumbled upon the same presentation last night.
Thanks once again.

4

In reply to dave_59:

Hi dave_59,

This is Lakshman Kumar. Can You explain the difference between export & imp with example. I know that difference is for imp, we have to write code separtely & for export we don’t need write any logic. is it write??

And also explain where we will use imp??

5

In reply to Lakshman4178:

Did you watch the link above?