Whatever I do, it doesn't work. Where did I go wrong?

UVM
1

I get syntax error while compiling uvm in vcs, I get syntax error in mux code although I tried many different rtl. where could I have made a mistake

vcs=("Following verilog source has syntax error :
“mux.v”, 1: token is ‘module’

mux.v code =

module  mux8x1(d0,d1,d2,d3,d4,d5,d6,d7,sel,out);
input d1;
input d2;
input  d3;
input  d4;
input  d5;
input  d6;
input  d7;
input  [2:0] sel;
output reg out;
always@(d0 or d1 or d2 or d3 or d4 or d5 or d6 or d7 or sel) begin
 case(sel)
3'b000: out=d0;
3'b001: out=d1;
3'b010: out=d2;
3'b011: out=d3;
3'b100: out=d4;
3'b101: out=d5;
3'b110: out=d6;
3'b111: out=d7;
endcase
end

endmodule
2

The d0 signal is in the port list, but you did not declare a direction. The simplest fix is to add a line:


module  mux8x1(d0,d1,d2,d3,d4,d5,d6,d7,sel,out);
input d0;

This is a common Verilog problem which can easily be avoided by using ANSI-style port declarations:


module  mux8x1 (
    input  d0,
    input  d1,
    input  d2,
    input  d3,
    input  d4,
    input  d5,
    input  d6,
    input  d7,
    input  [2:0] sel,
    output reg out
);

always @* begin
    case(sel)
        3'b000: out=d0;
        3'b001: out=d1;
        3'b010: out=d2;
        3'b011: out=d3;
        3'b100: out=d4;
        3'b101: out=d5;
        3'b110: out=d6;
        3'b111: out=d7;
    endcase
end
endmodule

I also shortened the sensitivity list to “@*” to avoid another common Verilog problem.

3

In reply to gsulliva:

I appreciate your help so much.