The d0 signal is in the port list, but you did not declare a direction. The simplest fix is to add a line:
module mux8x1(d0,d1,d2,d3,d4,d5,d6,d7,sel,out);
input d0;
This is a common Verilog problem which can easily be avoided by using ANSI-style port declarations:
module mux8x1 (
input d0,
input d1,
input d2,
input d3,
input d4,
input d5,
input d6,
input d7,
input [2:0] sel,
output reg out
);
always @* begin
case(sel)
3'b000: out=d0;
3'b001: out=d1;
3'b010: out=d2;
3'b011: out=d3;
3'b100: out=d4;
3'b101: out=d5;
3'b110: out=d6;
3'b111: out=d7;
endcase
end
endmodule I also shortened the sensitivity list to "@*" to avoid another common Verilog problem.
