I want to build a layer uvc, so I put the seq in sqr to receive item from upper layer driver,
this is just the first step
package my_pkg2;
import uvm_pkg::*;
`include "uvm_macros.svh"
class a_item extends uvm_sequence_item;
rand bit [7:0] a_data;
`uvm_object_utils_begin(a_item)
`uvm_field_int(a_data,UVM_ALL_ON)
`uvm_object_utils_end
function new(string name="a_item");
super.new(name);
endfunction
endclass
class a_seq extends uvm_sequence;
`uvm_object_utils(a_seq)
a_item a_item_h;
function new(string name="a_seq");
super.new(name);
endfunction
virtual task body();
a_item a_item_h;
uvm_sequence_item tmp;
tmp =create_item(a_item::get_type(),m_sequencer,"req");
$cast(a_item_h,tmp);
start_item(a_item_h);
a_item_h.randomize();
finish_item(a_item_h);
endtask
endclass
////////////////////////sequencer
class a_sequencer extends uvm_sequencer;
`uvm_component_utils(a_sequencer)
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
task run_phase(uvm_phase phase);
a_seq a_seq_h;
//phase.raise_objection(phase);
a_seq_h=new();
a_seq_h.start(this);
//phase.drop_objection(phase);
endtask
endclass
//////////////////////////driver
class a_driver extends uvm_driver;
`uvm_component_utils(a_driver)
uvm_sequence_item tr_q[$];
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
task main_phase(uvm_phase phase);
REQ tmp;
a_item a_item_h;
// forever begin
$display("--a_driver_h run0----$$$$$");
seq_item_port.get_next_item(tmp);
$cast(a_item_h,tmp);
`uvm_info(get_name(),$sformatf("%s",a_item_h.sprint()),UVM_LOW)
$display("--a_driver_h run--2----$$$$$");
seq_item_port.item_done();
$display("--a_driver_h run-----end----$$$$$");
// end
endtask
endclass
class a_env extends uvm_env;
`uvm_component_utils(a_env)
a_driver a_driver_h;
a_sequencer a_sequencer_h;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
a_driver_h=a_driver::type_id::create("a_driver_h",this);
a_sequencer_h = a_sequencer::type_id::create("a_sequencer_h",this);
endfunction
function void connect_phase(uvm_phase phase);
a_driver_h.seq_item_port.connect(a_sequencer_h.seq_item_export);
endfunction
endclass
class a_test extends uvm_test;
`uvm_component_utils(a_test)
a_env a_env_h;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
a_env_h=a_env::type_id::create("a_env_h",this);
//uvm_config_db#(uvm_object_wrapper)::set(this,
// "a_env_h.a_sequencer_h.main_phase",
// "default_sequence",
// a_seq::type_id::get());
endfunction
//function void connect_phase(uvm_phase phase);
//endfunction
//task run_phase(uvm_phase phase);
// a_seq a_seq_h;
// phase.raise_objection(phase);
// uvm_top.print_topology();
//// factory.print(); //打印override type
// a_seq_h =new();
// a_seq_h.start(a_env_h.a_sequencer_h);
//// #10ns;
// phase.drop_objection(phase);
//endtask
endclass
endpackage
module top_tb();
import uvm_pkg::*;
`include "uvm_macros.svh"
import my_pkg2::*;
initial begin
run_test();
end
endmodule
