I get this err when I try to start seq in the main_phase of sequencer , not in the test
In reply to designer007:
https://verificationacademy.com/forums/uvm/what-common.run-object-and-when-dose-it-try-drop-objection
I want to build a layer uvc, so I put the seq in sqr to receive item from upper layer driver,
this is just the first step
package my_pkg2;
import uvm_pkg::*;
`include "uvm_macros.svh"
class a_item extends uvm_sequence_item;
rand bit [7:0] a_data;
`uvm_object_utils_begin(a_item)
`uvm_field_int(a_data,UVM_ALL_ON)
`uvm_object_utils_end
function new(string name="a_item");
super.new(name);
endfunction
endclass
class a_seq extends uvm_sequence;
`uvm_object_utils(a_seq)
a_item a_item_h;
function new(string name="a_seq");
super.new(name);
endfunction
virtual task body();
a_item a_item_h;
uvm_sequence_item tmp;
tmp =create_item(a_item::get_type(),m_sequencer,"req");
$cast(a_item_h,tmp);
start_item(a_item_h);
a_item_h.randomize();
finish_item(a_item_h);
endtask
endclass
////////////////////////sequencer
class a_sequencer extends uvm_sequencer;
`uvm_component_utils(a_sequencer)
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
task run_phase(uvm_phase phase);
a_seq a_seq_h;
//phase.raise_objection(phase);
a_seq_h=new();
a_seq_h.start(this);
//phase.drop_objection(phase);
endtask
endclass
//////////////////////////driver
class a_driver extends uvm_driver;
`uvm_component_utils(a_driver)
uvm_sequence_item tr_q[$];
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
task main_phase(uvm_phase phase);
REQ tmp;
a_item a_item_h;
// forever begin
$display("--a_driver_h run0----$$$$$");
seq_item_port.get_next_item(tmp);
$cast(a_item_h,tmp);
`uvm_info(get_name(),$sformatf("%s",a_item_h.sprint()),UVM_LOW)
$display("--a_driver_h run--2----$$$$$");
seq_item_port.item_done();
$display("--a_driver_h run-----end----$$$$$");
// end
endtask
endclass
class a_env extends uvm_env;
`uvm_component_utils(a_env)
a_driver a_driver_h;
a_sequencer a_sequencer_h;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
a_driver_h=a_driver::type_id::create("a_driver_h",this);
a_sequencer_h = a_sequencer::type_id::create("a_sequencer_h",this);
endfunction
function void connect_phase(uvm_phase phase);
a_driver_h.seq_item_port.connect(a_sequencer_h.seq_item_export);
endfunction
endclass
class a_test extends uvm_test;
`uvm_component_utils(a_test)
a_env a_env_h;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
a_env_h=a_env::type_id::create("a_env_h",this);
//uvm_config_db#(uvm_object_wrapper)::set(this,
// "a_env_h.a_sequencer_h.main_phase",
// "default_sequence",
// a_seq::type_id::get());
endfunction
//function void connect_phase(uvm_phase phase);
//endfunction
//task run_phase(uvm_phase phase);
// a_seq a_seq_h;
// phase.raise_objection(phase);
// uvm_top.print_topology();
//// factory.print(); //打印override type
// a_seq_h =new();
// a_seq_h.start(a_env_h.a_sequencer_h);
//// #10ns;
// phase.drop_objection(phase);
//endtask
endclass
endpackage
module top_tb();
import uvm_pkg::*;
`include "uvm_macros.svh"
import my_pkg2::*;
initial begin
run_test();
end
endmodule
In reply to designer007:
Changing the argument to raise and drop objections should work.
a_seq a_seq_h;
phase.raise_objection(this);
a_seq_h=new();
a_seq_h.start(this);
phase.drop_objection(this);In reply to designer007:
You should fix your code first.
Please not:
(1) class a_seq extends uvm_sequence; is considered as a virtual sequence, because it is not paramerized with your seq_item.
(2) Your sequencer has to be paramereized also. class a_sequencer extends uvm_sequencer; is only correct for a virtual sequencer.
(3) Your driver is also not parameterized.
Please fix these issues and come back with the status.
In reply to chr_sue:
Hi chr_sue,
I know what you worried about,
the seq/seqr/driver all use uvm_sequence_item type ,
I used $cast to do the type convert, so the item seq ->sqr-> driver is uvm_sequence_item。
and questsim do not give error about the item type.
In reply to designer007:
This is not a syntactical problem but it might be a functional problem.
Following the basic guidelines is always a benefit.
BTW running your code does not show your error message.
Please remove your work library, recompile and run your code again.
In reply to chr_sue:
I tried ；
here is my makefile & whole log info
TESTNAME ?=a_test
all: work tb sim
work:
vlib work
tb:
vlog -f filelist.f
sim:
@vsim top_tb +UVM_TESTNAME=$(TESTNAME) +UVM_OBJECTION_TRACE -do "run -all;exit" -c -l $(TESTNAME).log -voptargs=+acc
clean:
rm -rf work *.log
vlib work
vlog -f filelist.f
QuestaSim-64 vlog 2020.4_1 Compiler 2020.11 Nov 6 2020
Start time: 18:56:15 on Feb 09,2021
vlog -f filelist.f
-- Compiling package my_pkg2
-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
** Note: (vlog-2286) ./my_pkg2.sv(3): Using implicit +incdir+/opt/mentor/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg
** Warning: ./my_pkg2.sv(29): (vlog-2240) Treating stand-alone use of function 'randomize' as an implicit VOID cast.
-- Compiling module top_tb
-- Importing package my_pkg2
Top level modules:
top_tb
End time: 18:56:16 on Feb 09,2021, Elapsed time: 0:00:01
Errors: 0, Warnings: 1
Reading pref.tcl
# 2020.4_1
# vsim top_tb "+UVM_TESTNAME=a_test" "+UVM_OBJECTION_TRACE" -do "run -all;exit" -c -l a_test.log -voptargs="+acc"
# Start time: 18:56:18 on Feb 09,2021
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: ./my_pkg2.sv(29): (vopt-2240) Treating stand-alone use of function 'randomize' as an implicit VOID cast.
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
# // Questa Sim-64
# // Version 2020.4_1 linux_x86_64 Nov 6 2020
# //
# // Copyright 1991-2020 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading mtiUvm.uvm_pkg(fast)
# Loading work.my_pkg2(fast)
# Loading mtiUvm.questa_uvm_pkg(fast)
# Loading work.top_tb(fast)
# Loading /opt/mentor/questasim/uvm-1.1d/linux_x86_64/uvm_dpi.so
# run -all
# ----------------------------------------------------------------
# UVM-1.1d
# (C) 2007-2013 Mentor Graphics Corporation
# (C) 2007-2013 Cadence Design Systems, Inc.
# (C) 2006-2013 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled
# with `UVM_NO_DEPRECATED undefined.
# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test a_test...
# UVM_ERROR @ 0: run [TEST_DONE_NOHIER] A non-hierarchical object, 'common.run' (<unknown>) was used in a call to uvm_test_done.raise_objection(). For this objection, a sequence or component is required.
# UVM_INFO @ 0: run [OBJTN_TRC] Object common.run raised 1 objection(s): count=1 total=1
# UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top added 1 objection(s) to its total (raised from source object common.run): count=0 total=1
# --a_driver_h run0----$$$$$
# UVM_INFO ./my_pkg2.sv(70) @ 0: uvm_test_top.a_env_h.a_driver_h [a_driver_h] ---------------------------------------------------------------------------------------
# Name Type Size Value
# ---------------------------------------------------------------------------------------
# req a_item - @624
# a_data integral 8 'h65
# begin_time time 64 0
# depth int 32 'd2
# parent sequence (name) string 5 a_seq
# parent sequence (full name) string 40 uvm_test_top.a_env_h.a_sequencer_h.a_seq
# sequencer string 34 uvm_test_top.a_env_h.a_sequencer_h
# ---------------------------------------------------------------------------------------
#
# --a_driver_h run--2----$$$$$
# --a_driver_h run-----end----$$$$$
# UVM_ERROR @ 0: run [TEST_DONE_NOHIER] A non-hierarchical object, 'common.run' (<unknown>) was used in a call to uvm_test_done.drop_objection(). For this objection, a sequence or component is required.
# UVM_INFO @ 0: run [OBJTN_TRC] Object common.run dropped 1 objection(s): count=0 total=0
# UVM_INFO @ 0: run [OBJTN_TRC] Object common.run all_dropped 1 objection(s): count=0 total=0
# UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (dropped from source object common.run): count=0 total=0
# UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (all_dropped from source object common.run): count=0 total=0
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1267) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 11
# UVM_WARNING : 0
# UVM_ERROR : 2
# UVM_FATAL : 0
# ** Report counts by id
# [OBJTN_TRC] 6
# [Questa UVM] 2
# [RNTST] 1
# [TEST_DONE] 1
# [TEST_DONE_NOHIER] 2
# [a_driver_h] 1
# ** Note: $finish : /opt/mentor/questasim/linux_x86_64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 0 ns Iteration: 226 Instance: /top_tb
# End time: 18:56:26 on Feb 09,2021, Elapsed time: 0:00:08
# Errors: 0, Warnings: 1
In reply to designer007:
And this is what I see in the log-file:
vsim top_tb +UVM_TESTNAME=a_test -voptargs=+acc
# vsim top_tb "+UVM_TESTNAME=a_test" -voptargs="+acc"
# Start time: 17:19:14 on Feb 08,2021
# ** Note: (vsim-8009) Loading existing optimized design _opt2
# Loading sv_std.std
# Loading mtiUvm.uvm_pkg
# Loading work.my_pkg2(fast)
# Loading mtiUvm.questa_uvm_pkg(fast)
# Loading work.top_tb(fast)
# Loading D:/SW/Questa/10.7e-prime/uvm-1.1d\win64\uvm_dpi.dll
run 0
# ----------------------------------------------------------------
# UVM-1.1d
# (C) 2007-2013 Mentor Graphics Corporation
# (C) 2007-2013 Cadence Design Systems, Inc.
# (C) 2006-2013 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled
# with `UVM_NO_DEPRECATED undefined.
# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test a_test...
# --a_driver_h run0----$$$$$
# UVM_INFO designer007.sv(70) @ 0: uvm_test_top.a_env_h.a_driver_h [a_driver_h] ---------------------------------------------------------------------------------------
# Name Type Size Value
# ---------------------------------------------------------------------------------------
# req a_item - @624
# a_data integral 8 'h65
# begin_time time 64 0
# depth int 32 'd2
# parent sequence (name) string 5 a_seq
# parent sequence (full name) string 40 uvm_test_top.a_env_h.a_sequencer_h.a_seq
# sequencer string 34 uvm_test_top.a_env_h.a_sequencer_h
# ---------------------------------------------------------------------------------------
#
# --a_driver_h run--2----$$$$$
# --a_driver_h run-----end----$$$$$
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 4
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Questa UVM] 2
# [RNTST] 1
# [a_driver_h] 1
# ** Note: $finish : D:/SW/Questa/10.7e-prime/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 0 ns Iteration: 223 Instance: /top_tb
# 1
# Break in Task uvm_pkg/uvm_root::run_test at D:/SW/Questa/10.7e-prime/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430
Interesting. I’m running Questa 10.7e (64 bit) on Windows.
In reply to chr_sue:
I find out that
in sequencer
phase.raise_objection(phase); //err
if change (phase) to (this) then ok, in linux.
but I confuse that (this) means the parameter that of the run_phase args or mean the sequencer?
In reply to designer007:
This shows the arguments of the function raise_objection:
virtual function void raise_objection (
uvm_object obj,
string description = “”,
int count = 1
)
The 1st arg is never phase. It points to the object where it is called, i.e. ‘this’.
If you are calling this in the sequencer it is the sequencer.