What is std_logic_vector16(15 downto 0)?

UVM
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I came across a VHDL DUT with two data types that I am unfamiliar with:


: in  std_logic_vector16(15 downto 0);
: in  std_logic_vector32(31 downto 0);

Can someone explain what these data types are? Also, can std_logic_vector16 and std_logic_vector32 connect to a UVM testbench?

Thanks!

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In reply to bstephen:

Without seeing the source code, I’d guess that there is a package that defines the types std_logic_vector16/32 and that this package is used by the VHDL RTL code in question.

You can share packages between VHDL + SystemVerilog but it requires a switch to be added to compilation and that will be vendor specific.

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In reply to graeme_jessiman:

Thanks for that response. I think you pointed me in the right direction. I will check out the package file.