What should be the value of an un-initialized realtime variable? Should this time-0 race condition should hang the simulation?

UVM
1

My interface file contains the following, Assume this as my clock interface.
//--------------------------------------------------
realtime m_clk_period; // un-initialized
initial m_ref_clk = 1’b0;
always #(m_clk_period/2) m_ref_clk = ~m_ref_clk;
……………….
……………….
……………….
//--------------------------------------------------
// And my Driver run_phase method contains the following section
// Contains the following
//--------------------------------------------------
task clk_driver::run_phase (uvm_phase phase);
super.run_phase (phase);
vif.m_clk_period = m_config.clk_period;

// FYI : I fully understand this is not a good coding practice, and I should have done it in connect phase but still my question is different //
……………….
……………….
……………….
//-------------------------------------------------
Between UN-initialized /realtime/ variable in always block

And my initialization statement in /run_phase/, causing time-0 race.

How should a simulator handles such events? Enter irrespective of the order and always keep poling for initialization? Or just enter the statement and get stuck there for the rest of your file. Irrespective of initialization happens in the same time stamp.?

2

In reply to shrac123:

Table Table 6-7—Default variable initial values in the IEEE 1800-2017 SystemVerilog LRM says the default value of a real is 0.0.

There is no race here—you have a zero-delay loop. When you call run_test(), sticks in a few #0’s in before starting the phases to make sure all initial bocks have a chance to execute first. You should write your clock generator as

initial wait(m_clk_period>0) forever #(m_clk_period/2) m_ref_clk = ~m_ref_clk;