Hi,
For the sake of the question, imagine the following scenario.
I have a register that changes and should be checked after a sequence of milestones happens. For example,
- A value should be written using AHB on Add1 address
- Some value should be written on Add3 using AXI
- B value should be written on AHB on Add2 address
- CHECK after this sequence of events that the register address Add3 has the value X.
The check could be more complex because, in between of these events, other AHB, AXI access from other instances can write.
In our team there are two first ideas to implement this check but maybe you can offer me other better methodologies.
First idea: This allows re-usability according to
https://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_guidelines/detail/
which says that all checkers should be implemented not "in the sequence that generates the stimulus" but in a component that is dependent only on the monitored bus.
The idea is to collect or flag all different monitored TLM transactions that match the sequence above (collected or flagged as class members of the scoreboard) from AHB, AXI. Then, a checker is created that is called each time that the 3rd step happens. The checker will verify if previous steps are also correctly done and then it will check the register value at Add3.
The disadvantage of this methodology is the extra effort to code the checker.
On the other hand, the second idea, is easier to implement but from the methodology point of view will not be re-usable (if you replace your sequence with another DUT you dont have the checker)
You can see that somehow on the following article of Mentor
http://www.design-reuse.com/articles/32778/systemverilog-uvm-sequence-task-equivalence.html
The second solution would be to just perform the steps 1,2,3 in your sequence and the do a read of the register value from the sequence and check that has the correct value X.
In the article of Mentor it is suggested that sequences can also be used as "checkers" and they explicitly write and read a value from the sequence not to control only the stimulus but to perform comparisons and checks of register values.
What is the correct approach?.
In the verification academy i haven't seen a clear answer to that yet. If there is a clear methodology, then could you point me to that?.
Is there any other better solution?.
Lastly, it would be good a methodology not only for register checkers, because the question applies to general checkers. In any case, if there is a solution for this using the API of the uvm register model (e.g. quirky register?) then i would appreciate it.
Looking forward your answer
Best regards,
Jonathan
