What is the purpose of bus_req.end_event.wait_on(); in uvm_reg_map::do_bus_write

UVM
,
1

Hi ,

What is the significant of bus_req.end_event.wait_on(); in uvm_reg_map::do_bus_write

task uvm_reg_map::do_bus_write (uvm_reg_item rw,
uvm_sequencer_base sequencer,
uvm_reg_adapter adapter);

…
…

if (rw.parent != null && i == 0)
rw.parent.mid_do(rw);
rw.parent.finish_item(bus_req);
bus_req.end_event.wait_on();
if (adapter.provides_responses) begin
uvm_sequence_item bus_rsp;
uvm_access_e op;
// TODO: need to test for right trans type, if not put back in q
rw.parent.get_base_response(bus_rsp);
adapter.bus2reg(bus_rsp,rw_access);
end

…

endtask

2

In reply to uvm_novice:

In some pipelined protocols, finish_item returns before the transaction is complete. This line waits for the transaction to complete.