What is the output of the tlm_fifo model?

Hii,
I am beginner of the UVM. I am try to code a producer consumer transaction via the tlm fifo. But I am not get the expected value.So how to improve my code .
Tell your suggestion

And my code is below

import uvm_pkg::*;
`include "uvm_macros.svh"


class tlm_seq_item extends uvm_sequence_item;
  
  rand bit a;
  rand byte b;
  rand int c;

  `uvm_object_utils_begin(tlm_seq_item)
     `uvm_field_int(a,UVM_ALL_ON)
     `uvm_field_int(b,UVM_ALL_ON)
     `uvm_field_int(c,UVM_ALL_ON)
   `uvm_object_utils_end

  function new(string name="tlm_seq_item");
     super.new(name);
   endfunction
 
 endclass

class tlm_producer extends uvm_component;
  
    `uvm_component_utils(tlm_producer)

    uvm_blocking_put_port #(tlm_seq_item) my_put_port;

    function new(string name="tlm_produce", uvm_component parent=null);
     super.new(name,parent);
     my_put_port=new("my_put_port",this);
     endfunction
 
  virtual task run_phase(uvm_phase phase);
    for(int i=0;i<5;i++)
      begin
        tlm_seq_item seq;
        seq=tlm_seq_item::type_id::create("seq",this);
        seq.randomize();
        seq.print();
          //$display("IT IS PRODUCER");
        my_put_port.put(seq);
        `uvm_info("SEND",$sformatf("the data ia i=%d %p",i,seq),UVM_LOW)
        #10;
       end

   endtask  

  endclass

class tlm_consumer extends uvm_component;
   
  `uvm_component_utils(tlm_consumer) 

   uvm_blocking_get_port #(tlm_seq_item) my_get_port;

    function new(string name="tlm_consumer",uvm_component parent=null);
       super.new(name,parent);
       my_get_port=new("my_get_port",this);
     endfunction

    virtual task run_phase(uvm_phase phase);
        for(int i=0;i<5;i++)
         begin
           tlm_seq_item seq;
           seq=tlm_seq_item::type_id::create("seq",this);
           my_get_port.get(seq);
           `uvm_info("REC",$sformatf("recieved packet i=%0d %p",i,seq),UVM_LOW)
          end
      endtask
  endclass

class tlm_env extends uvm_env;
 
   `uvm_component_utils(tlm_env)

    uvm_tlm_fifo #(tlm_seq_item) my_fifo;

    tlm_producer producer;
    tlm_consumer consumer;

    function new (string name="tlm_env",uvm_component parent=null);
       super.new(name,parent);
      endfunction

    function void buid_phase(uvm_phase phase);
       super.build_phase(phase);
       producer=tlm_producer::type_id::create("producer",this);
       consumer=tlm_consumer::type_id::create("consumer",this);
         //$display("builded or producer and consumer");
      endfunction

    function void connect_phase(uvm_phase phase);
       producer.my_put_port.connect(my_fifo.put_export);
       consumer.my_get_port.connect(my_fifo.get_export);
      endfunction

    virtual task run_phase(uvm_phase phase);
        phase.raise_objection(this);
         #1000;
        phase.drop_objection(this);
      endtask

  endclass     

module top;
    tlm_env env;
    
    initial begin
      env=new();
      $display("calling");
      run_test();
      $display("end calling");
      end
  endmodule

In reply to Rajaraman R:

I did not check all your code, but the question is what you get?
For Scenarios like this there is a sequencer/driver connection adequate.
Both have all ports and exports you need.
See examples here: https://verificationacademy.com/cookbook/cookbook-code-examples#UVM_Examples:#UVM_Examples:#UVM_Examples:

BTW on the same level of hierarchy you can only connect ports with exports.