What is meaning of UVM_REG_BLOCK?

UVM
1

Hello

I have one question…

Q1) Are the registers accessible through one interface composed of one UVM_REG_BLOCK? or cna it consist of multiple UVM_REG_BLOCK?

Thanks in advance

2

In reply to suhyun:

You can build a hierarchy of UVM Reg blocks so at the top level there will be one interface. That assumes your design has a single top-level block of registers with one or more interfaces. But you could have independent reg blocks if your design has completely separate address spaces with separate sets of registers.