I have read about both of these terms but not able to get the crystal clarity that what is not being done by SoC verification, that pre silicon is needed ?
In reply to Sing hda:
I have read about both of these terms but not able to get the crystal clarity that what is not being done by SoC verification, that pre silicon is needed?
My understanding is the following, but I welcome comments:
- SoC verification This is the verification of the chip to ensure that it would work in the system with the hardware and software environment. Emphasis is on making sure that all the partitions, interfaces, and software are compatible. Timing is not verified, as it is generally done at the RTL or higher level. Emulators may also be used.
- Pre-silicon emulation/validation This verification is more about lower level, gate-level, and getting all the stuff ready for fabrication. That means doing things like self-check through scanning and signature *(by that setting up the scan tests and getting the signature needed so that when the chip is fabbed, it is a quick way to verify that it is OK.
*. Since gates are involved, maybe a final timing is done. Also, sometimes, at this pre-silicon stage, some interface buffers may be redefined. Because of these changes, equivalence testing is also needed. Note that at this stage, there most likely be no system/software checks.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
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