What is difference between 'include and import and use?

Hi,
`include:

We have a uvm environment,we have a package file with in the package file we declare the all file like include "dut.sv",include “driver.sv”, all components etc…

import:
with in the component we are write import package import pkg_1::; import uvm_pkg::;

Iam not understand what is the difference and what is the use of.

The include construct is used to include a file in just one place. include is typically used to include .svh files when creating a package file. If one needs to reference a type or other definition, then ‘import’ is used to bring the definition into scope.

Why one shouldn’t use include, is because type definitions are scope specific. A type defined in two scopes using the same include file are not recognised as being the same. If the type is defined in one place, inside a package, then it can be properly referenced by importing that package.

See my blog post: SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons