What is the best way to implement a wait in a UVM sequence, for an internal DUT signal to assert before proceeding to send sequence items to the driver?

What is the best way to implement a wait in a UVM sequence, for an internal DUT signal to assert before proceeding to send sequence items to the driver?

My coworker is trying this approach:

In the TB top module, instancing an interface with a single logic signal.
Doing a continuous assign of the signal in the interface to the internal DUT signal (Using the full hierarchical path to the internal DUT signal)
i.e. assign if.trigger_signal = tb_top.DUT.internal_signal
Doing a UVM config_db “set” to pass the virtual interface.

In the Sequence, task body(), do a UVM config_db “get” to get a handle to the interface.
Do a @(vif.trigger_signal) to block until the internal DUT signal asserts.

We’re having trouble getting this approach to work, and wanted to know if there is any issue with this approach itself?
Is there a better approach?

In reply to obajaj.arm:

All timing related activities has to be done in the driverand not in the sequence/sequencer. The driver is retrieving a seq_item when necessary. This will be created in 0 time.
There is no need to have events or clock signals somewhere in the sequence.