Hello,
I would like to be able to wait for a signal until it reach a specific value, in a body() task of a sequence.
The signal is an internal within my DUT, so I want to reach it using hierarchical reference string (like it is done with uvm_hdl_read).
I thought of writing do while loop and use uvm_hdl_read, e.g.:
do
#10 // or @(posedge clk)
while (uvm_hdl_read(“dut.int_sig”) > 3)
But I think it will cost a lot in simulation time/performance.
Do you have a better idea?
Mody
In reply to modymiller:
What you are doing is useless, because athe syequence and the sequncer does not know anything about timing and clock cycles. All timing aspects will be handled in the driver/monitor.
If you want to control the behavior of your seq_items you can do this passing back a response from the driver to the sequencer/sequence. Look here for the corresponding code example. It becomes a little bit more complicates because you want to observe an internal signal. You could add this signal to your virtual interface and connecting it from the toplevel module.
In reply to chr_sue:
When using regular Agent you have a point. But I need something else.
Example: Let say I want to check interrupt cause specifically a CRC error.
Generating a stimuli to do this from DUT boundaries is too complicated.
So, I want to change the value if an internal signal at a specific time and get the required error.
For that I need to wait for a specific value (wait for the right time) then change the value.
Also pushing away from using bind interface to simplify the solution and keep it at test level.
Thanks,
In reply to modymiller:
Again the test doeas not know anything about our timing and the clock cycles. How do you observe an internal signal depends on what you prefer. bind is one option, uvm_hdl_read another one and using a hierarchical path is an third one. As I said you can add this internal signal to your SV inteface and observing in the driver what happens there. If the condzion happens you can create your response and put it back to the sequence.
In reply to modymiller:
Yes this is terribly inefficient. Use bind to create an interface that has a task that waits on your signal. Then call that task from your sequence.
In reply to modymiller:
I found out that Cadence has it own system task called xm_mirror, which mirrors source signal value to destination signal.
You set the source and destination signals using hierarchical reference.
once you launch it every change in source signal value is shown in the destination.
This enabled me to do what I wanted.
One draw back is you can’t use dynamic objects as inputs. I.e. can’t use it in class.
Simple resolution to this is to call xm_mirror from an interface (which I instantiate in the TB) and pass it’s pointer to the sequence.
I wonder whether this will reach UVM-SV, but is there any thing like this in other EDA’s?