I would like to be able to wait for a signal until it reach a specific value, in a body() task of a sequence.
The signal is an internal within my DUT, so I want to reach it using hierarchical reference string (like it is done with uvm_hdl_read).
I thought of writing do while loop and use uvm_hdl_read, e.g.:
#10 // or @(posedge clk)
while (uvm_hdl_read("dut.int_sig") > 3)
But I think it will cost a lot in simulation time/performance.
Do you have a better idea?