Waiting for @posedge clk

Hi,

I have to get the data after checking for a signal which goes high after some clock cycles. When i see the results in the waveform i can see it goes high after some clock cycles (after the arrival of the data). So, when this signal goes high, the data needs to be written in a file.

task run_phase(uvm_phase phase);
      forever begin
          @(posedge vif.clk)
          begin   
             trans.valid_out <= vif.dut_clk.valid_out;
                if(vif.vip_clk.valid_out == 1) begin
                fd = $fopen("data_txt", "w"); 
                $fwrite(fd, "%b", trans.valid_out);  
                $display("valid_out=%d", trans.valid_out);
                trans.ciphertext[0] <= vif.dut_clk.ciphertext[0];
                $display("ciphertext=%h", trans.ciphertext[0]);
               end
             end
          end  
   endtask

But the “if condition” never becomes true. So, what is the correct way to check for the valid_out signal so that it is checked at every clock cycle.

In reply to shankar_logic:

What kind of data type is vif.vip_clk?

In reply to shankar_logic:
Please use code tags when posting code. I have added them for you. (top-right button over the text-box you type in)

If vip_clk is a clocking block, you need to make sure valid_out is declared as an inout to be able read and write it. Also, use @(vif.vif_clk) instead of @(posedge vif.clk).

If vif_clk is not a clocking block, you need to show the definitions of all signals involved.

Sure Dave i will take care of such things while posting any query next time. Thanks

Actually vif is the virtual interface and vif_clk is the clocking block declared inside the interface.

In reply to shankar_logic:

If you are using a clocking block then you have to synchronize on it:
@(posedge vif.clk) has to be replaced by
@(posedge vif.vip_clk)

BTW what is dut_clk?

ifndef INTERFACE_SV define INTERFACE_SV

interface intf(input bit clk);
wire [255:0] key;
wire [127:0] data;
wire [127:0] ciphertext;
wire valid_in;
wire valid_out;

clocking vip_clk@(posedge clk);
output data;
output key;
output valid_in;
input ciphertext;
input valid_out;
endclocking

clocking dut_clk@(posedge clk);
input data;
input key;
input valid_in;
output ciphertext;
output valid_out;
endclocking

modport vip_cb(clocking vip_clk);
modport dut_cb(clocking dut_clk);

endinterface
`endif

Actually there are two clocking blocks in this case, one is for the vip which is operating on the driver signals and one is on the DUT side which is operating on the Monitor

In reply to shankar_logic:

I do not understand why you need 2 clocking blocks. A clocking block is a means to avoid races between the testbench and the DUT, i.e. if you have only 1 clock you need only 1 clocking block!
I believe here is your problem, because you are using 2 clocking blocks for 1 clock.