I have to get the data after checking for a signal which goes high after some clock cycles. When i see the results in the waveform i can see it goes high after some clock cycles (after the arrival of the data). So, when this signal goes high, the data needs to be written in a file.
task run_phase(uvm_phase phase);
forever begin
@(posedge vif.clk)
begin
trans.valid_out <= vif.dut_clk.valid_out;
if(vif.vip_clk.valid_out == 1) begin
fd = $fopen("data_txt", "w");
$fwrite(fd, "%b", trans.valid_out);
$display("valid_out=%d", trans.valid_out);
trans.ciphertext[0] <= vif.dut_clk.ciphertext[0];
$display("ciphertext=%h", trans.ciphertext[0]);
end
end
end
endtask
But the “if condition” never becomes true. So, what is the correct way to check for the valid_out signal so that it is checked at every clock cycle.
In reply to shankar_logic:
Please use code tags when posting code. I have added them for you. (top-right button over the text-box you type in)
If vip_clk is a clocking block, you need to make sure valid_out is declared as an inout to be able read and write it. Also, use @(vif.vif_clk) instead of @(posedge vif.clk).
If vif_clk is not a clocking block, you need to show the definitions of all signals involved.
Actually there are two clocking blocks in this case, one is for the vip which is operating on the driver signals and one is on the DUT side which is operating on the Monitor
I do not understand why you need 2 clocking blocks. A clocking block is a means to avoid races between the testbench and the DUT, i.e. if you have only 1 clock you need only 1 clocking block!
I believe here is your problem, because you are using 2 clocking blocks for 1 clock.