Wait

Hi,

UVM support the uvm_hdl_force, uvm_hdl_force_time, uvm_hdl_read() etc. but it don’t have similar method for wait. How can it be done ?

I can’t use SV wait because i want to pass the path from C which can be different from test to test and SV won’t allow wait with string changing during run time.

wait(path_name, value);

In reply to Rahul Patel:

Doing what you want requires deep knowledge of the SystemVerilog’s VPI. You’ll need to set up a value change callback on the path you want wait on, then have it toggle a bit local to where you want to have the wait when that path reaches the value you’re looking for.

I have a DVCon 2016 paper that might help you get started.