Hello,
I would like to understand better the NOACCESS policy for some fields in UVM1.2.
Let’s take an example with a RAL model.
class my_reg extends uvm_reg;
`uvm_object_utils(my_reg)
rand uvm_reg_field fld_w1t;
function new(string name = "my_reg ");
super.new(name, 32, build_coverage(UVM_NO_COVERAGE));
add_coverage(build_coverage(UVM_NO_COVERAGE));
endfunction
virtual function void build();
this.fld_w1t= uvm_reg_field::type_id::create("fld_w1t");
this.fld_w1t.configure(.parent(this), .size(1), .lsb_pos(0), .access(**"W1T"**), .volatile(0), .reset(1'd0), .has_reset(1), .is_rand(1), .individually_accessible(0));
endfunction
endclass
class my_reg_block extends uvm_reg_block;
`uvm_object_utils(my_reg_block )
rand my_reg my_reg0;
uvm_reg_map apb;
function new(string name = "my_reg_block ");
super.new(name, UVM_NO_COVERAGE);
endfunction
virtual function void build();
apb= create_map("apb", 'h0, 4, UVM_LITTLE_ENDIAN, 1); default_map = apb;
my_reg0= sasa_model_MID_REG0::type_id::create("my_reg0");
my_reg0.configure(this, null, "my_reg0"); my_reg0.build();
apb.add_reg( my_reg0, 'h800, "WO"); // Register as WO (makes more sense since only Write-only fields) => **Field seen as NOACCESS ???**
//apb.add_reg( my_reg0, 'h800, "RW"); // Register as RW => Fields seen as W1T, as expected
lock_model();
endfunction
endclass
What I don’t understand is that if I set the Access Right for Register “my_reg” to WO, which according to me make sense
since this register does only contain Write-Only fields (actually only one field with W1T access), then, I get a NOACCESS field access for fld_w1t
Looking at the UVM1.2 uvm_reg_field code is consistent with this behavior (see below) but I don’t understand why this is defined like this ?
function string uvm_reg_field::get_access(uvm_reg_map map = null);
string field_access = m_access;
if (map == uvm_reg_map::backdoor())
return field_access;
// Is the register restricted in this map?
case (m_parent.get_rights(map))
"RW":
// No restrictions
return field_access;
"RO":
case (field_access)
"RW", "RO", "WC", "WS", "W1C", "W1S", "W1T", "W0C", "W0S", "W0T", "W1" : field_access = "RO";
"RC", "WRC", "W1SRC", "W0SRC", "WSRC" : field_access = "RC";
"RS", "WRS", "W1CRS", "W0CRS", "WCRS" : field_access = "RS";
"WO", "WOC", "WOS", "WO1": field_access = "NOACCESS";
// No change for the other modes
endcase
"WO": // <---
case (field_access)
"RW", "WO": field_access = "WO";
default: field_access = "NOACCESS"; // <-- This applies to my W1T field
// No change for the other modes
endcase
default:
begin
field_access = "NOACCESS";
`uvm_warning("RegModel", {"Register '",m_parent.get_full_name(),
"' containing field '",get_name(),"' is mapped in map '",
map.get_full_name(),"' with unknown access right '", m_parent.get_rights(map), "'"})
end
endcase
return field_access;
endfunction: get_access
=> Can someone explain this to me please ?
And also : is there a way to “force” the field access policy to W1T in the case the Register Rights are WO ?
Many thanks in advance,