I am trying to run a testcase which performs UVM predefined Register Tests. I used
+define+UVM_REG_ADDR_WIDTH=32
+define+UVM_REG_DATA_WIDTH=32
in the run script to overwrite the default address and datawidth for the UVM Predefined sequences(which is 64).
These defines are not being accepted by vlog(and they still remain 64 bits). Has anyone encountered this issue before? Could you please let me know how/where should I specify these defines for the Simulator to accept these defines?
Te Register model I generated is 32 bit wide
create_map("", 'h0, 4, UVM_LITTLE_ENDIAN, 1);
Run script:
+incdir+/verilog_src/uvm-1.1d/src \
+define+UVM_REG_ADDR_WIDTH=32 \
+define+UVM_REG_DATA_WIDTH=32 \
/verilog_src/uvm-1.1d/src/uvm_pkg.sv \
Error Message :
# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_map.svh(1996) @ 40000: reporter [uvm_reg_map] Reading address 'hffffffff80000fe8 via map
As you can see, the error message shows the address being 64 bits wide instead of 32 bits
