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  • vlog not accepting +define for UVM_REG_ADDR_WIDTH/UVM_REG_DATA_WIDTH

vlog not accepting +define for UVM_REG_ADDR_WIDTH/UVM_REG_DATA_WIDTH

UVM 5390
#uvm 217 uvm register model 12
gowthamnirmalraj
gowthamnirmalraj
Full Access
3 posts
August 23, 2017 at 12:51 pm

I am trying to run a testcase which performs UVM predefined Register Tests. I used

+define+UVM_REG_ADDR_WIDTH=32
+define+UVM_REG_DATA_WIDTH=32

in the run script to overwrite the default address and datawidth for the UVM Predefined sequences(which is 64).

These defines are not being accepted by vlog(and they still remain 64 bits). Has anyone encountered this issue before? Could you please let me know how/where should I specify these defines for the Simulator to accept these defines?

Te Register model I generated is 32 bit wide
create_map("", 'h0, 4, UVM_LITTLE_ENDIAN, 1);

Run script:
+incdir+/verilog_src/uvm-1.1d/src \
+define+UVM_REG_ADDR_WIDTH=32 \
+define+UVM_REG_DATA_WIDTH=32 \
/verilog_src/uvm-1.1d/src/uvm_pkg.sv \

Error Message :
# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_map.svh(1996) @ 40000: reporter [uvm_reg_map] Reading address 'hffffffff80000fe8 via map

As you can see, the error message shows the address being 64 bits wide instead of 32 bits

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Solution

Solution

Tudor Timi
Tudor Timi
Full Access
333 posts
August 23, 2017 at 11:41 pm

In reply to gowthamnirmalraj:

If I remember correctly, QuestaSim comes with a pre-compiled UVM library (it was called something like mtiUvm), which it automatically loads when it notices you import uvm_pkg into your code. You'll have to look in the manual how to force it to compile a UVM version with other defines.

Constrained random thoughts on SystemVerilog and e: http://blog.verificationgentleman.com/

gowthamnirmalraj
gowthamnirmalraj
Full Access
3 posts
August 23, 2017 at 11:57 pm

In reply to Tudor Timi:

Yes, you are correct. By default it imports a pre-compiled UVM library. I had to re-compile the uvm_pkg for overriding the default defines with the ones I specified and then it works.

Tudor Timi
Tudor Timi
Full Access
333 posts
August 24, 2017 at 12:39 am

In reply to gowthamnirmalraj:

Just make sure that you still get the vendor extension (transaction recording and such) in there (if you care about it, that is). The built-in UVM comes with these goodies, but compiling a pure Accellera version won't have these.

Constrained random thoughts on SystemVerilog and e: http://blog.verificationgentleman.com/

Patrick A.
Patrick A.
Full Access
5 posts
March 26, 2018 at 5:09 am

In reply to gowthamnirmalraj:

Quote:
In reply to Tudor Timi:

Yes, you are correct. By default it imports a pre-compiled UVM library. I had to re-compile the uvm_pkg for overriding the default defines with the ones I specified and then it works.

Hi,
I also encountered the same problem and was wondering how you were able to override the default defines of the pre-compiled UVM library. Could you please tell me how?

Patrick A.
Patrick A.
Full Access
5 posts
March 26, 2018 at 7:35 pm

In reply to gowthamnirmalraj:

Hi gowthamnirmalraj,

While searching the forums for other solutions to this problem, I noticed that you probably replied to my question earlier. However, I cannot see the full content of your reply in this thread. I'm not sure what could be the problem but could you please post your answer again in this thread? I'd appreciate it very much, thanks!

gowthamnirmalraj
gowthamnirmalraj
Full Access
3 posts
March 27, 2018 at 8:36 am

In reply to Patrick A.:

You need to re-compile the UVM base class library "uvm_pkg"(as part of vlog command) and use these defines(+define+UVM_REG_ADDR_WIDTH=32 +define+UVM_REG_DATA_WIDTH=32) along with them for it to take effect.

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