Virtual Sequencers: Cannot assign an unpacked type to a packed type

UVM
1

Hello,

I am trying to use virtual sequencers, but in the assignment of the handles in the virtual sequencer class to the actual sequencers, I keep getting this error:

Loading work.tinyalu(rtl)#1

** Error: (vsim-3567) tb_classes/env_w_agent.svh(36): No field named ‘sequencer_h’.

Time: 0 ns Iteration: 0 Region: /tinyalu_pkg File: tinyalu_pkg.sv

** Error: (vsim-3567) tb_classes/env_w_agent.svh(37): No field named ‘sequencer_h’.

Time: 0 ns Iteration: 0 Region: /tinyalu_pkg File: tinyalu_pkg.sv

** Error: (vsim-7065) tb_classes/env_w_agent.svh(37): Illegal assignment to type ‘reg’ from type ‘class work.tinyalu_pkg::sequencer’: Cannot assign an unpacked type to a packed type.

Time: 0 ns Iteration: 0 Region: /tinyalu_pkg File: tinyalu_pkg.sv

** Error: (vsim-7065) tb_classes/env_w_agent.svh(36): Illegal assignment to type ‘reg’ from type ‘class work.tinyalu_pkg::sequencer’: Cannot assign an unpacked type to a packed type.

Time: 0 ns Iteration: 0 Region: /tinyalu_pkg File: tinyalu_pkg.sv

The problem is that the assignment of

function void connect_phase(uvm_phase phase);
v_sqr.add_sequencer.sequencer_h = add_agent.sequencer_h;
v_sqr.sub_sequencer.sequencer_h = sub_agent.sequencer_h;
endfunction
in the env_w_agent.svh file, is somehow an “unpacked-to-packed” assignment…?

I am quite confused as to why I am getting this error and cannot find any help from previous posts…

Any help would be greatly appreciated, thanks!

Code:



class env extends uvm_env;
   `uvm_component_utils(env);
   
   virtual_sequencer v_sqr;
   tinyalu_agent #("abfm")         add_agent;
   tinyalu_agent #("sbfm")        sub_agent;
   
   function new (string name, uvm_component parent);
      super.new(name,parent);
   endfunction : new

   function void build_phase(uvm_phase phase);
      
      add_agent  = tinyalu_agent#("abfm")::type_id::create("add_agent",this);
      sub_agent  = tinyalu_agent#("sbfm")::type_id::create("sub_agent",this);
	  v_sqr 	 = virtual_sequencer::type_id::create("m_v_sqr", this);
	  
   endfunction : build_phase
   
   function void connect_phase(uvm_phase phase);
	    v_sqr.add_sequencer.sequencer_h = add_agent.sequencer_h;
	    v_sqr.sub_sequencer.sequencer_h = sub_agent.sequencer_h;
   endfunction
   
endclass

class tinyalu_agent #(string BFM_NAME="bfm") extends uvm_agent;
   `uvm_component_param_utils(tinyalu_agent#(BFM_NAME))

   driver #(BFM_NAME)       driver_h;
   sequencer     		    sequencer_h;

function new (string name, uvm_component parent);
   super.new(name,parent);
endfunction : new  

function void build_phase(uvm_phase phase);
	sequencer_h  = sequencer::type_id::create("sequencer_h",this);
	driver_h     = driver#(BFM_NAME)::type_id::create("driver_h",this);
endfunction : build_phase

function void connect_phase(uvm_phase phase);
     driver_h.seq_item_port.connect(sequencer_h.seq_item_export);
endfunction : connect_phase

endclass : tinyalu_agent

class virtual_sequencer extends uvm_sequencer #(uvm_sequence_item);
`uvm_component_utils(virtual_sequencer)

sequencer add_sequencer;
sequencer sub_sequencer;

function new(string name = "virtual_sequencer", uvm_component parent = null);
  super.new(name, parent);
endfunction

endclass: virtual_sequencer

class sequencer extends uvm_sequencer #(sequence_item);
`uvm_component_utils(sequencer)

// Standard UVM Methods:
function new(string name="sequencer", uvm_component parent = null);
  super.new(name, parent);
endfunction

endclass: sequencer

virtual class tinyalu_base_test extends uvm_test;

   env       env_h;
   
   function void build_phase(uvm_phase phase);
      env_h = env::type_id::create("env_h",this);
   endfunction : build_phase

   function new (string name, uvm_component parent);
      super.new(name,parent);
   endfunction : new

endclass

class add_test extends tinyalu_base_test;
   `uvm_component_utils(add_test);
   
   add_sequence add_seq;

   task run_phase(uvm_phase phase);
      add_seq = new("add_seq");
      phase.raise_objection(this);
      add_seq.start(null);
      phase.drop_objection(this);
   endtask : run_phase


   function new (string name, uvm_component parent);
      super.new(name,parent);
   endfunction : new

endclass

package tinyalu_pkg;
   import uvm_pkg::*;
`include "uvm_macros.svh"
`include "sequence_item.svh"  
`include "abstract.svh"
`include "sequencer.svh"
`include "virtual_sequencer.svh" 
`include "add_sequence.svh"

`include "driver.svh"
`include "tinyalu_agent.svh"
`include "env_w_agent.svh"

`include "tinyalu_base_test.svh"
`include "add_test.svh"
   
endpackage : tinyalu_pkg
2

In reply to ce_2015:

The error messages tell you what the problem is. Always look at the first error and focus on that:

** Error: (vsim-3567) tb_classes/env_w_agent.svh(36): No field named ‘sequencer_h’.

Time: 0 ns Iteration: 0 Region: /tinyalu_pkg File: tinyalu_pkg.sv

** Error: (vsim-3567) tb_classes/env_w_agent.svh(37): No field named ‘sequencer_h’.

Time: 0 ns Iteration: 0 Region: /tinyalu_pkg File: tinyalu_pkg.sv

The class ‘virtual_sequencer’ contains ‘add_sequencer’ and ‘sub_sequencer’. These two sequencers don’t contain a field named ‘sequencer_h’.

In your connect_phase(), you want:


   function void connect_phase(uvm_phase phase);
	    v_sqr.add_sequencer = add_agent.sequencer_h;
	    v_sqr.sub_sequencer = sub_agent.sequencer_h;
   endfunction
3

You’re absolutely right! I thought those first two errors were the result of the second two errors. My mistake! How embarrassing… Thanks for your help!