Virtual register

what is the difference between UVM_REG and UVM_VREG

In reply to venky970:

A virtual register is a collection of fields, overlaid on top of a memory, usually in an array. The semantics and layout of virtual registers comes from an agreement between the software and the hardware, not any physical structures in the DUT.

https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1a/html/files/reg/uvm_vreg-svh.html

It seems there is no good example of virtual register shipped with UVM. I’m actually porting UVM to python/cocotb, and would like to add an example of using virtual registers. I bumped into them while dealing with some SystemRDL files which were generating virtual registers.

Does anyone have a good usecase/example how to actually use the virtual registers in verification? And any example when one should re-allocate the virtual register to another memory region from the current one? I’ve read what the user guide and documentation states about virtual registers, but has anyone actually used them in their verification projects?