I'm struggling with this problem for quite some time.
In module I have defined virtual interface for axi lite which I want to use for DUT configuration.
Then I have created model_config component, which contains several configuration tasks. In build phase I check whether the intreface exists in uvm_config_db and it does! But as I want to access interface and configure some component in DUT, verification ends with:
Break in Task std/mailbox::get at /opt/modelsim/modeltech/linux_x86_64/../verilog_src/std/std.sv line 41
If I comment out code within the configuration tasks, which is accessing the interface, no error occurs.