Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • Questa Verification IQ - April 11th
      • Continuous Integration
      • SystemVerilog Assertions
      • SoC Design & Functional Safety Flow
      • 2022 Functional Verification Study
      • Design Solutions as a Sleep Aid
      • CDC and RDC Assist
      • Formal and the Next Normal
      • Protocol and Memory Interface Verification
      • Webinar Calendar
    • On-Demand Library

      • Practical Flows for Continuous Integration
      • Lint vs Formal AutoCheck
      • The Three Pillars of Intent-Focused Insight
      • Formal Verification Made Easy
      • Fix FPGA Failures Faster
      • HPC Protocols & Memories
      • FPGA Design Challenges
      • High Defect Coverage
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Complex Safety Architectures
      • Data Independence and Non-Determinism
      • Hierarchical CDC+RDC
      • All On-Demand Recordings
    • Recording Archive

      • Aerospace & Defense Tech Day
      • Exhaustive Scoreboarding
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • Visualizer Debug Environment
      • Preparing for PCIe 6.0: Parts I & II
      • Automotive Functional Safety Forum
      • Siemens EDA Functional Verification
      • Improving Your SystemVerilog & UVM Skills
      • All Webinar Topics
    • Conferences & WRG

      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Verification Horizons - July 2022
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Academy News
      • Contact Us
    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
Ask a Question
UVM
  • Home
  • Forums
  • UVM
  • virtual interface and multiple drivers (signal drivers not UVM drivers)

virtual interface and multiple drivers (signal drivers not UVM drivers)

UVM 6670
UVM 206 interface 11 virtual interface 8
verif_learner
verif_learner
Forum Access
395 posts
March 21, 2018 at 7:20 am

I have an interface that has modports for UVM driver component and also for DUT.
The UVM driver modport has signals that are all output except for one signal that is input (driven by the DUT).
As expected, the DUT has all input signals except one signal that is output from the DUT.

Now, I am planning to use the DUT modport interface in the monitor also.
The monitor needs all output signals driven by the UVM driver. It does not need the one signal that is output of DUT.

In this scenario, the monitor is going to have a modport with one output signal. Will this create multiple driver condition.
I went through the LRM but could not find any description as to how drivers for virtual interfaces are created and how multiple drivers are resolved.

Thanks,

Replies

Log In to Reply
cgales
cgales
Forum Moderator
1956 posts
March 21, 2018 at 7:53 am

In reply to verif_learner:

I find that modports provide no real benefits, yet add unnecessary complexity, especially when used in a UVM environment. Because of this, I see no reason to use them.

You will typically only get warnings/errors when you multiply drive a signal by assign statements or connecting multiple registers. Port connections won't generally create issues since the input/output notation are merely suggestions.

verif_learner
verif_learner
Forum Access
395 posts
March 25, 2018 at 9:24 am

In reply to cgales:

I thought modports are very convenient and a way to specialize a given interface.
Any digital HW block has signal of 3 types (input, output, input_output).
Without modport, this basic direction of any signal cannot be specified.

This is my understanding. Let me know what issues you see.

cgales
cgales
Forum Moderator
1956 posts
March 25, 2018 at 10:33 am

In reply to verif_learner:

Modports are useful when designing synthesizable hardware blocks. For verification, they are of limited use and add confusion and complexity.

When interfaces used for verification are connected to the DUT, you will typically instantiate the interface, then connect it to the DUT as below:

interface my_if(input bit clk, input bit rst);
  wire a;
  wire b;
endinterface
 
my_if my_if_i(.clk(clk), .rst(rst));
 
dut dut_i(.clk(clk),
          .rst(rst),
          .a(my_if_i.a),
          .b(my_if_i.b)
);

Using a modport adds no additional benefit. You need to add another hierarchical name that isn't necessary.

uvm_user235
uvm_user235
Forum Access
11 posts
April 04, 2018 at 1:00 am

In reply to cgales:

Hi,
What about clocking block? I think it is more widely used.
Please let know your thoughts on skew also.

Regards,
Chandan

verif_learner
verif_learner
Forum Access
395 posts
August 09, 2018 at 8:13 am

In reply to cgales:

Quote:
In reply to verif_learner:

Modports are useful when designing synthesizable hardware blocks. For verification, they are of limited use and add confusion and complexity.
[/systemverilog]

I am opening this thread.
When modports are used in agents, one can make the mistake of driving input ports etc.
So, I am wondering as to why this is not an advantage in using modports

chr_sue
chr_sue
Full Access
3850 posts
August 09, 2018 at 9:01 am

In reply to verif_learner:

Quote:
In reply to cgales:

Quote:
In reply to verif_learner:

I am opening this thread.
When modports are used in agents, one can make the mistake of driving input ports etc.
So, I am wondering as to why this is not an advantage in using modports

modports adding nothing else as checking of the data direction. But this is one thing you'll see this immediately when you are driving an output indicated by an error.
I have never used modports in all my projects.

verif_learner
verif_learner
Forum Access
395 posts
August 10, 2018 at 8:41 am

In reply to chr_sue:

Quote:
In reply to verif_learner:

Quote:
In reply to cgales:

Quote:
In reply to verif_learner:

I am opening this thread.
When modports are used in agents, one can make the mistake of driving input ports etc.
So, I am wondering as to why this is not an advantage in using modports

modports adding nothing else as checking of the data direction. But this is one thing you'll see this immediately when you are driving an output indicated by an error.
I have never used modports in all my projects.

Thanks. Can you give a sample code for an interface that has signals and clocking blocks and no modports?

I can use it as a reference. I have always used signals from interface using the modports. So, I would like to see one without it.

chr_sue
chr_sue
Full Access
3850 posts
August 10, 2018 at 11:06 am

In reply to verif_learner:

I want to ask only 1 question: what is the difference between a signal driver and a uvm_driver?

Siemens Digital Industries Software

Siemens Digital Industries Software

#TodayMeetsTomorrow

Portfolio

  • Cloud
  • Mendix
  • Electronic Design Automation
  • MindSphere
  • Design, Manufacturing and PLM Software
  • View all Portfolio

Explore

  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Customer Stories
  • Partners
  • Trust Center

Contact

  • VA - Contact Us
  • PLM - Contact Us
  • EDA - Contact Us
  • Worldwide Offices
  • Support Center
  • Give us Feedback
© Siemens 2023
Terms of Use Privacy Statement Cookie Statement DMCA