Verification of the state machine

UVM
1

Hi All,

I am new to the verification, can some please help regarding state machine verification.

  1. What can be the basic test cases that can be written to verify the state machine?
    2)For example if I have a sequence detector with sequence 1011 what can be the possible test cases?

Thanks…

2

1.) apply stimulus to detect whole sequence.
2.) apply reset in parallel to stimulus for state machine, it should get reset to initial state.
3.) check every state transition using testcases.

3

In reply to juhi_p:

Thanks for the reply.

I have question how to write the test cases for the every state transaction.
If possible could you please provide any link which will help in understanding clearly regarding the writing of the test cases for the state machine

4

No, I am not aware of any material for same.

5

In reply to narendrareddy:

In reply to juhi_p:
Thanks for the reply.
I have question how to write the test cases for the every state transaction.
If possible could you please provide any link which will help in understanding clearly regarding the writing of the test cases for the state machine

In most cases your state machine is somewhere inside of your design, i.e. you cannot reach the input signals to your state machine directly. For this reason you have to measure which transitions you have covered.

6

In reply to chr_sue:

yes, we generally use code coverage for same.

7

In reply to juhi_p:

In reply to chr_sue:
yes, we generally use code coverage for same.

Code coverage does not help in this case. What you need is functional coverage. Theree you can define the transitions between the states of your FSM.

8

In reply to chr_sue:
but code coverage has FSM transitions and FSM states. If DUT has state machine then we can use the same? or is it advised to have functional coverage for same?

9

In reply to juhi_p:

My two cents here, from my experience in different projects I consider using functional coverage is more portable since you can use this coverage across different projects and tools, using tool’s specific files to describe the valid state transitions or to exclude them can become tedious especially if you need use more than one EDA simulator, also with new version of the same tool it could become deprecated. In the end is up to your requirements and and resources to decide what approach suits you best.

Just keep in mind that if you implement the functional coverage then you need to make sure you connect the collectors to the right hierarchy, either using bindings or interfaces + UVM, etc
HTH,

-R

10

In reply to juhi_p:

In reply to chr_sue:
but code coverage has FSM transitions and FSM states. If DUT has state machine then we can use the same? or is it advised to have functional coverage for same?

FSM code coverage is not specific enough to judge the quality of your FSM.
Functional coverage has to be defined by yourself. You can adopt this to your special needs.
To check the correct function of your FSM you can use SV Assertions.