Hi Verification Forum Desk,
I’ve some basic queries which I need to get clarify, though I have some prior knowledge on this. Following are my queries.
Thanks in Advance.
Regards,
Partha
Q)What are the guidelines to write a Verification Plan/Test Plan? Is there any standard format to be followed for this?
You can write the Testplan in a notepad/Spread Sheet, every company has its own way !
-BR
Hash
Hi Partha,
Let’s take your questions one at a time:
What is Verification Flow (from scratch to completion)?
The “verification flow” is the entire process you go through to verify your design, from planning, through actual testing - using simulation, emulation and/or formal verification - debug and analysis to determine if you actually tested everything. It is referred to as a flow because it is never just a single step. Your process flows from one test to another, and usually from block-level verification for each piece of your design up to system-level verification where you exercise the entire design.
What is the difference between Verification Plan and Test Plan?
Not much. These two terms are usually interchangeable, although we prefer “Verification Plan” because it can include information about desired metrics to determine completion. In either case, the plan will be organized around design requirements, with an outline of how each specific requirement will be tested. This usually includes deciding on the tool/strategy for each requirement and in the case of simulation often includes a definition of the coverage metric (often a SystemVerilog covergroup) that will be used to determine if it was, in fact, tested. Please see our Verification Planning and Management video course for more information.
What is the difference between RTL Verification, VIP Verification and SoC Verification?
RTL verification refers to verifying actual RTL code, usually written in Verilog, SystemVerilog or VHDL. As a general rule of thumb, the term usually refers to what is also called “block-level verification” where you’re verifying a piece of your design that will later be assembled into the overall system.
“VIP Verification” isn’t a term that is typically used, since “VIP” means “Verification Intellectual Property,” which usually refers to a pre-verified piece of verification infrastructure (usually a UVM component of some kind) that provides what you need to verify certain standard protocols. In general, VIP refers to any piece of a verification environment (also called a testbench) that can be reused.
What are the guidelines to write a Verification Plan/Test Plan? Is there any standard format to be followed for this?
Please see the video course mentioned above.
Good luck,
-Tom
In reply to tfitz:
Hello Tom,
Thanks a lot for you concern and reply.
Still I have one query that related to previously asked 3rd question.
As you have said above “VIP Verification” isn’t a term that is typically used, since “VIP” means “Verification Intellectual Property,”. That is fine but now a days in industry people frequently use a term “IP Verification”, What does it mean ?
One more Question is :
When we don’t have real RTL, Specification is usually given to us to develop TestBench. For example- Any master-slave protocols. At that time we develop Testbench Environment for both Master as well as Slave and verify each of their functionality and then either of the RTL and TestBench(Master RTL & Slave TestBench) we use for Verification.
Which kind of verification is it called in case of no RTL we have and verifying our Master and Slave by each other ?
In reply to Piyush Dodiya:
You are right that each piece of verification IP needs to be itself verified, so you could call this “IP Verification.” My point is that it doesn’t really matter what you call it. The scenario you outline where you test a master-side VIP against a slave-side VIP is quite common. We like to say that “one person’s design IP is another person’s verification IP.” With your scenario, you would eventually replace the slave-side VIP with RTL and use the master-side VIP to verify the RTL, or vice versa. We usually call the process of verifying the master/slave VIP in the absence of RTL “building a testbench.” ;-)