Verification of dut.how to acess

i am new to uvm and system verilog based verification.i just wanted to know how the actual output and expected output do we get?i think we should send stimulus to dut and monitor its output.but without knowing the internals of dut how can we send stimulus to it?should we write the same logic as written in dut in order to verify to get the expected result? please clear my doubt.

In reply to mohan chandra pradhan:

Hi,

You have a specification. The spec is implemented by designers as dut and verif engineers as BFM model. You drive stimulus to both BFM and DUT. The output of DUT is actual response and BFM is a expected response. Compare both responses in Scoreboard to validate your design

In reply to Anudeep J:

Thanks for your reply… But in bfm do we write the same logic or code written in dut? Do we have to know the internals of dut to apply the stimulus?

In reply to mohan chandra pradhan:

Yes. Specification is common thing for both Designers and Verif engineers.Designers make their DUT on their understanding of the spec and verif on their understanding.It may be same or may not be same. For a verif engineer, DUT is just a black box. you should know only the inputs and outputs and what type of stimulus to be driven.

In reply to Anudeep J:

OK… How stimulus is given to dut? I mean seeing it as a black box, how to connect verif engineer’s developed code? If inputs and outputs are already known den dat known outputs can be used as actual response?

In reply to mohan chandra pradhan:

Hi,

You can find all the things in the below link. Further if you have any queries, you can post it here

https://verificationacademy.com/courses