Verfication Testbench Architecture specific

I was trying to finalize a VIP Architecture for my USB-DUT . I was thinking of taking advantage of sequence layering . In protocol interface(UTMI) I’ll build a monitor that will convert pin level activities to a Transaction level packets . On input side I’ll have AHB Agent that will configure DUT for specific transaction/sequence of transaction. He I’m confused that whether to build a higher level sequence(For re-usability ) and by mean of translator_seq I’ll convert it to AHB level sequence .
In input monitor should I again convert AHB signal to Higher level transaction and send it to scoreboard or just directly send higher_level (originally generated for higher level seq) to scoreboard ?