hi
property variable_delay(counter);
@ (negedge clk) disable iff(rst_n !== 1’b1) (data[35] == 1’b1 && data[34] == 1’b0 && error[5:0] == 6’b000000) |-> ##[50:150] $rose (result) |-> ##[8:70] $fell (result);
endproperty
i want to give variable delay ##[8:70] instead of this delay
below code i tried but getting compilation error
always @(regedge clk)
logical [31:0]min;
property variable_delay(counter);
@ (negedge clk) disable iff(rst_n !== 1’b1) (data[35] == 1’b1 && data[34] == 1’b0 && error[5:0] == 6’b000000) |-> ##[50:150] $rose (result) |-> ##[min] $fell (result);
endproperty
constant_varaible :assert property (variable delay) uvm_info("SFC_check", $sformatf("recieving any pause"),UVM_LOW)else uvm_error(“SFC_check”, $sformatf(“dut recieving any pause without malframe”));