Hi,
in my design we have several register blocks and several interfaces. all/some of the blocks are accessible from these interfaces. In two block of the block some registers have overlapping offsets, usually this issue is solved by setting different base address to different block. the issue here is that there isnt ‘different base address’ the difference comes from different propriety of the bus. e.g. bar .
the question is how do I model it into the adapter bus2reg function uvm_reg_bus_op output? the ‘bar’ propriety is available only at the function level (as part of the transaction), currently only the uvm_reg_bus_op.address has some decoding info, so inorder to bypass the issue we had to create false mapping in one of the blocks, by using some of the unused bits to hold the ‘bar’ info. but I’m not happy with it at all since I have to ‘give’ the hack to all reg model users e.g. checker/s.
how can I avoid this problem?
thx
Uriel