In source code of uvm-1.2 file “uvm_reg_fifo.svh” (https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/src/reg/uvm_reg_fifo.svh), the implementation of write() and read() methods are empty. Some very weird result comes out when I try to use this class.
In reply to Huang Yunlong:
See what the standard is saying.
18.8 uvm_reg_fifo
This special register models a DUT FIFO accessed via write/read, where writes push to the FIFO and reads
pop from it.
Back-door access is not enabled, as it is not yet possible to force complete FIFO state, i.e., the write and read
indexes used to access the FIFO data.
18.8.1 Class declaration
class uvm_reg_fifo extends uvm_reg
read and write are inherited from uvm_reg : class uvm_reg_fifo extends uvm_reg!
In reply to chr_sue:
when I try to access a uvm_reg_fifo with write(), I always get an error message: “Needs Update”,“Must call update() after set() and before write()”. I inspect the source code and find a reason.
Here’s an abstract of the UVM source code:
task write(); // inherited from uvm_reg
set(); // increase the counter by 1
pre_write(); // report error if the counter is not 0
do_write();
post_write();
endtask;
function set();
fifo.push_back();
cnt++;
endfunction;
task pre_write();
if(cnt != 0)
$error();
endtask;
In reply to Huang Yunlong:
Whan you are calling a set this brings your RAL model out of sync. Befor doing anything else you have to synchronize your RAL model again. The corresponding command is update(). Finally a write doing bot: performing a set() and calling update().
See the details here: Registers | Verification Academy