Uvm_reg_fifo broken?

Has anyone ever had a play with the uvm_reg_fifo? The implementation seems really broken.

I was having issue similar to the ones here.
So I started digging

Basically, if you call FIFO.set() then FIFO.update(), then it gets itself into and loop which only breaks when it has completely filled the FIFO.

There is an example uvm_reg_fifo in
uvm-1.1d/examples/simple/registers/models/fifo_reg
which compiles and runs. However, by doing only a slight modification (see patch below) and printing out some extra info, it looks to me as if this test is broken as well.

I have tried various workarounds (using the ‘write’ function, etc) but they all have other issues (in fact, most of the code in uvm_reg_fifo seems broken).

I would think its unlikely that I am the first person to come up against these issues. Am I missing something? Has anyone else seen this before? Does anybody have any workarounds?

Kind regards,
Craig

– a/tb_run.sv 2016-07-29 14:25:11.914182476 +0100
+++ b/tb_run.sv 2016-07-29 14:28:55.506348579 +0100
@@ -91,13 +91,15 @@
`uvm_info(“FIFO Example”,
$sformatf(“Initializing FIFO reg of max size %0d with set()…”,max), UVM_LOW)

  •  expected = new[max];
    
  •  expected = new[7];
    
     // SET - preload regmodel; remodel now has full FIFO; DUT still empty
     foreach (expected[i]) begin
       data = $urandom;
       expected[i] = data;
       FIFO.set(data);
    
  •    `uvm_info("FIFO Example",
    
  •      $sformatf("data[%0d]:%x\n", i,data), UVM_LOW)
     end
    
     `uvm_info("FIFO Example",
    

@@ -105,6 +107,10 @@

   // UPDATE - write regmodel contents to DUT; DUT now has full FIFO
   FIFO.update(status);
  •  foreach(FIFO.fifo[i]) `uvm_info("FIFO Example",
    
  •   $sformatf("entry[%0d]:%x\n", i,FIFO.fifo[i]), UVM_LOW)
    
  •  if (status == UVM_NOT_OK) begin
       `uvm_fatal("FIFO Update Error", "Received status UVM_NOT_OK updating DUT")
     end
    

In reply to craig_ensilica:

Side comment: After a quick read of the uvm_reg_fifo code, it seems to me that the concepts of desired and mirrored values are mushed together. This would support your point that the implementation is broken. You could implement your own fifo reg class and do it right.