I encounter some UVM_WARININGs while doing register reads/writes:
UVM_WARNING: Setting the value of field “AAA” while containing register BBB is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem
It seems there is a trying to write field AAA of register BBB while another thread is already reading the value from this register. I can not understand how it occurs, since apb driver is get only one transaction and send it at one time since it is blocking port. Even there are 2 threads, which are trying to access the same field, the apb seqr will arbitrate, send only one transaction to driver. How can it occur?
Another question is how to resolve it? Can anybody give me some suggestion, much appreciated! Thanks in advance!
It is possible that you are trying to predict the value when a write access is done.
Wait while function .is_busy from your uvm_reg returns 0, than predict.
Thanks for replying, I have already resolved this issue. I found that in my env， when I write something to a register, actually I do
model.dut_rf.reg1.data.set(8’h55);
model.dut_rf.reg1.write(status,UVM_FRONTDOOR,.parent(this));
when I read something from a register, actually I do
model.dut_rf.reg1.read(status,rdata,UVM_FRONTDOOR,.parent(this));
when you call the function set, it will check whether current reg has been accessed by other operations such as read or write. If yes, this warning will be reported. How I resolve this warning:
Something like you said:
wait(model.dut_rf.reg1.m_is_busy == 1’b0); // wait m_is_busy = 0, then access the register.
model.dut_rf.reg1.data.set(8’h55);
model.dut_rf.reg1.write(status,UVM_FRONTDOOR,.parent(this));
I have the same issue. I know it’s been some time since you replied to this post but could you please elaborate on why update instead of write? What does it imply?
Then you are doing something twice.
Doing a ‘write’ modifies the register content in the RAL and in the DUT. That’s it.
Using ‘set’ mofifies only the RAL reg. A following ‘write’ writes again the the RAl and then to the DUT register.
W:: UVM/FLD/SET/BSY: Setting the value of field “XXX” while containing register “YYY” is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
In my case, I have instantiated register model twice because I have replicated module in RTL and differentiated both module by base_address. When I am disabling the one module, read/write is working fine on another module and vice-versa. This issue is occurring only while trying to access both modules simultaneously. RAL instance are different, base address are different than don’t know how this warring is shouting.
Can someone please guide me if I am missing something to differentiate both module?