Hi, I am facing a problem while reading register value
my adpater code is : -
class my_adapter extends uvm_reg_adapter;
`uvm_object_utils(my_adapter)
function new(string name = "my_adapter");
super.new(name);
endfunction
//------------------------------------------------------------------------------------------------------------------
virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
my_txn pkt;
if(transaction_type)
$cast(pkt, factory.create_object_by_type(transaction_type, "", "pkt"));
else pkt = my_txn::type_id::create("pkt");
pkt.randomize();
if(rw.kind==UVM_READ) pkt.wr_read = 'b0;
else pkt.wr_read= 'b1;
pkt.data = (rw.kind==UVM_READ) ? 0:rw.data;
pkt.address= rw.addr;
return pkt;
endfunction: reg2bus
//--------------------------------------------------------------------------------------------------------------------
virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
my_txn pkt;
if (!$cast(pkt, bus_item))
uvm_report_error("ERROR","Provided bus_item is not of the correct type");
else begin
uvm_report_info("BUS_2_REG",{"\n", pkt.sprint()}, UVM_NONE);
rw.kind = (pkt.wr_read == 'b0) ? UVM_READ : UVM_WRITE ;
rw.addr = pkt.address;
rw.data = (rw.kind==UVM_READ) ? pkt.data : 0;
rw.status = UVM_IS_OK;
end
endfunction: bus2reg
endclass: my_adapter
my env connections is : -
agent agent_h;
agent_sequencer hl_reg_sqr;
uvm_reg_predictor #(uvm_sequence_item) m_predictor;
my_adapter my_adapter_h;
-------------------------
-------------------------
if (env_cfg.reg_map_i != null) begin
env_cfg.reg_map_i.set_sequencer(hl_reg_sqr, my_adapter_h);
env_cfg.reg_map_tap.set_auto_predict(0);
m_predictor_i.map = env_cfg.reg_map_i;
m_predictor_i.adapter = my_adapter_h;
agent_h.req_aport.connect(m_predictor_i.bus_in);
end
Test case
class access_reg extends test_base;
`uvm_component_utils(access_reg)
// new
// ---
rd_reg_model rd_reg_model_h;
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
//
function void build_phase(uvm_phase phase);
super.build_phase(phase);
rd_reg_model_h = rd_reg_model ::type_id::create("rd_reg_model_h ");
endfunction : build_phase
function void connect_phase(uvm_phase phase);
rd_reg_model_h.reg_model = reg_model_all; // reg_model_all is created on test_base class
endfunction : connect_phase
task run_phase (uvm_phase phase);
rd_reg_model_h.start(env.hl_reg_sqr);
endtask : run_phase
endclass : access_reg
sequence :-
class rd_reg_model_seq extends uvm_sequence;
`uvm_object_utils (rd_reg_model_seq)
ral_block_MEM reg_model;
bit [31:0] rdata;
extern function new(string name="");
extern virtual task body();
endclass : rd_reg_model_seq
//-------
function rd_reg_model_seq::new(string name="");
super.new(name);
endfunction : new
//-------
task rd_reg_model_seq::body();
uvm_status_e status;
//STATUS_CFG having RW access
reg_model.STATUS_CFG.read(status, rdata, .parent(this)); // reset value of STATUS_CFG 'h700
$display(“received value is == %0h”,rdata); // getting rdata as zero.
If(status == UVM_NOT_OK) `uvm_error(get_type_name”error occurred”)
endtask : body
But when I am reading the STATUS_CFG register I am getting 'h0 instead of 'h700 and also uvm_status is UVM_IS_OK
similarly write operation is doing well(data is written in to register successfully) problem is only on read
can anyone tell me why I am getting this issue?
Thanks