In reply to abhishek403:
Actually I was doing UVM_RAL. can anyone help me out from these 4 doubts.
1. what is the exact difference between uvm_reg_sequence and uvm_sequence #(uvm_sequence_item) in frontdoor access..?
2. what is the difference between write_reg (or write) and read_reg (or read) methods and where we need to use these methods exactly..?
3. For backdoor access which components and objects we need and where we will declare peek_reg and poke_reg methods..?
4. How the bus2reg and reg2bus gets called in frontdoor access. Is it implicitly called by uvm or we need to call explicitly these methods..?
(1) class uvm_reg_sequence #(type BASE = uvm_sequence #(uvm_reg_item)) extends BASE;
Instead of uvm_reg_sequence you can use uvm_sequence #(uvm_reg_item).
(2) write writes data to the register and read reads the content of a register. The read performs a mirror() (reading from DUT and a get, reading value from mirror. The write makes a set (modifying the mirror reg) and a updates (writes the desired value to the DUT).
(3) peek and poke are methods provided by the register layer. peek provides always a backdoor read. poke provides a backdoor write. Using the backdoor does not need the adapter and the predictor, but backdoor does not provide the whole functionality of the register layer. In the consequence you cannot remove them from your testbench.
(4) bus2reg and reg2bus are performing the interface from the generich UVM register commands to the commands of your agent, used for accessing the registers. You don't have to call them, but you have to provide all components belonging to the register layer.