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  • UVM_Phasing Clarification needed

UVM_Phasing Clarification needed

UVM 6946
UVM_PHASE 11 run_phase() 5
MaheshBabu
MaheshBabu
Full Access
9 posts
November 09, 2015 at 10:55 am

Hi, I have a base testcase where I use config, main phases and end the test. I have env where I have main , report and final phases.
Is it really necessary to have report and Final phase in my base test and extended tests ?
Because I see my testcase hangs after the main_phase and doesn't continue further even after adding set_drain_time for said time.

Also if I have set of testcases(10) extended from base, do I need to add report and final phase for all the tests, since all the tests are in my compile list.

Can someone help me on this.

Best Regards,
Prince

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dave_59
dave_59
Forum Moderator
11281 posts
November 09, 2015 at 10:59 pm

The report and final phases are function calls, and cannot block. The only reason you you could get a hang in those phases is if you had coding error that executed an infinite loop.

The UVM does not require those phases, and it really does not matter if your base, or extended, or both have those phases. That is upt to the testbench architect.

Most likely you have a component stuck in the run_phase. Without seeing any code, it is going to be hard to help you. And you might have too much code to show in this forum. I suggest you try some of the UVM debugging techniques or use your tools interactive debugger.

— Dave Rich, Verification Architect, Siemens EDA

MaheshBabu
MaheshBabu
Full Access
9 posts
November 13, 2015 at 1:34 am

In reply to dave_59:
Hi Dave,

Thank you very much for the reply.
I could able to debug, due to forever loop inside the objection in driver main_ph has caused the problem and it is working now.

Bst Rgds,
MB

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