Hi folks,
I have been writing a code for a router.
The router contains the following ports
FROM THE SOURCE NETWORK
clock,
resetn,
packet_valid,
data_in,
TO SOURCE NETWROK
error & busy
FROM DESTINATION NETWORK
read enable
TO DESTINATION NETWORK
valid_out
data_out
I have created a virtual interface with clocking blocks and the following is the code.
logic [7:0]d_in;
logic pv;
logic rst;
logic err;
logic busy;
logic vo;
logic re;
logic [7:0]dout;
//-----------------------------------
bit clk; // The clock needs to be specified here
assign clk=clock;
// DUV Modport
modport DUV_MP (input d_in,pv,rst,clk,re,
output dout,vo,err,busy);
//-------------------------------
clocking wr_drv_cb@(posedge clock);
default input #1 output #1;
output d_in;
output rst;
output pv;
input err;
input busy;
endclocking
clocking rd_drv_cb@(posedge clock);
default input #1 output #1;
output re;
endclocking
clocking wr_mon_cb@(posedge clock);
default input #1 output #1;
input d_in;
input rst;
input pv;
input busy;
input err;
endclocking
clocking rd_mon_cb@(posedge clock);
default input #1 output #1;
input re;
input dout;
endclocking
modport WRDRV_MP(clocking wr_drv_cb);
modport RDDRV_MP(clocking rd_drv_cb);
modport WRMON_MP(clocking wr_mon_cb);
modport RDMON_MP(clocking rd_mon_cb);
endinterface
///------------------------------------------------
How do I collect it in my collect_task of monitor?
task router_wr_monitor::collect_data();
write_xtn data_sent;
data_sent=write_xtn::type_id::create("data_sent");
@(posedge vif.wr_mon_cb.clk);
wait((!vif.wr_mon_cb.busy) && vif.wr_mon_cb.pv)
data_sent.header=vif.wr_mon_cb.d_in; // nt using continuous assignment
// @(posedge vif.wr_mon_cb.clk);
@(posedge clock);
foreach(data_sent.payload[i])
begin
wait(!vif.wr_mon_cb.busy)
data_sent.payload[i]=vif.wr_mon_cb.d_in;
//@(posedge vif.wr_mon_cb.clk);
@(posedge clock);
end
wait(!vif.wr_mon_cb.busy && !vif.wr_mon_cb.pv)
data_sent.parity=vif.wr_mon_cb.d_in;
`uvm_info("ROUTER_WR_MONITOR",$sformatf("printing from monitor \n %s",data_sent.sprint()),UVM_LOW)
endtask
///
This is the top file:
//module top;
import router_pkg::*;
import uvm_pkg::*;
`include "uvm_macros.svh"
// When we are including the interface, we sync the interface TB & DUT with a clock.
//FOR THIS WE NEED TO GENERATE THE CLOCK IN TB
bit clock;
always
#10 clock=!clock;
// Instantiate ROUTER INTERFACE WITH CLOCK AS INPUT
router_if in0(clock);
//Instantitate RTL ROUTER_DUT & PASS INTERFACE INSTANCE AS ARGUMENT
//router_top dut(in0);
router_if in1(clock);
router_if in2(clock);
router_if in3(clock);
router_top D1(.packet_valid(in0.pv),.resetn(in0.rst),.err(in0.err),.busy(in0.busy),.data(in0.d_in),
.vld_out_0(in1.vo),.read_enb_0(in1.re),.data_out_0(in1.dout),
.vld_out_1(in2.vo),.read_enb_1(in2.re),.data_out_1(in2.dout),
.vld_out_2(in3.vo),.read_enb_2(in3.re),.data_out_2(in3.dout),
.clock(in0.clk));
Please help me out!
Lemme know if you need more inputs