In reply to chr_sue:
Hi, So if I want to just use the uvm_mem feature of RAL and I dont have any memory being defined in DUT, can this still be used. Because once I write in the memory and try to read back, it is reading the value as 0s and not what I have written.
Will this approach work, or should I use only the system verilog (memories, i.e. queues or associative arrays etc).