Hi ,
Even though i pass +UVM_MAX_QUIT_COUNT=1000 , simulation stops after 5 errors. My understanding is simulation should stop after 1000 errors. may i know, what is the issue?
Thanks
Saravanan
Hi ,
Even though i pass +UVM_MAX_QUIT_COUNT=1000 , simulation stops after 5 errors. My understanding is simulation should stop after 1000 errors. may i know, what is the issue?
Thanks
Saravanan
In reply to uvm_novice:
The +UVM_MAX_QUIT_COUNT=1000 is the threshold for up to max 1000 errors. When simulation reaches to 1000 uvm_error then it will exit from the simulation. It’s possible that you don’t get any uvm_error and your test passes even thought after passing this switch. This is expected behavior only.
In general, you don’t want to set +UVM_MAX_QUIT_COUNT to 1000. As per your expectations, you can set 1 to 10 which can help to save simulation cycle.
In reply to bdreku:
Did you check if there is an
set_report_max_quit_count = 5;
statement in your code?
In reply to chr_sue:
Hi ,
My testcase fails with monitor error. It is monitor issue. but still i want to run my testcase up to end. so i passed switch +UVM_MAX_QUIT_COUNT=1000 but simulation stops after 5 errors
In reply to uvm_novice:
You can set the simulator quit count from the SV code and from the command line.
I asked you if there is in your code the quit count set.
See my last post.
And please check if you do not face a fatal. A fatal stops the simulation immediately.